Abstract: A pipelined scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.

Abstract: A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.

Abstract: Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and a transmission line electrically coupling the interface circuit to a memory controller, wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller.

Abstract: A method and apparatus for compacting test responses containing unknown (X) values in a scan-based integrated circuit using an X-canceling multiple-input signature register (MISR) to produce a known (non-X) signature. The known (non-X) signature is obtained by selectively exclusive-ORing (XORing) together combinations of MISR bits which are linearly dependent in terms of the unknown (X) values using a selective XOR network.

Abstract: A medical pump with an improved continuity low flow delivery system and method for use with a pumping chamber, for example in a cassette, is disclosed. The pump includes a pump drive for exerting a force on the pumping chamber and a sensor for sensing the force/pressure exerted by the pump drive on the pumping chamber. The pump drive position sensor senses the position of the pump drive. The medical pump also includes a processing unit and a memory having a programming code adapted to calculate the rate of change of the sensed force/pressure values and determine whether the rate of change of the sensed force/pressure values meets a rate of change threshold. Once the rate of change threshold is met, the programming code is adapted to calculate a remaining pump drive travel value for determining how much farther the pump drive should travel before the end of an effective pump cycle.

Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.

Abstract: Measurements are taken of moisture, BTU/lb (British Thermal Units per pound), ash, forms of sulfur, volatile material, grindability, and absorption properties of any of a wide variety of mine-run solid fuels. Using that information, a dry electromagnetic process technology has been developed that can be controlled and monitored to selectively alter and enhance solid fuel properties for the application in question. Specific changes include altering the mechanical structure and chemical composition of solid fuels such as coal, coal coke or petroleum coke, increasing the BTU/lb to optimum levels, decreasing all forms of sulfur, and decreasing ash, while maintaining the BTU/lb of the fuels. A new family of solid fuel designer coals not found in nature can be produced via these methods and apparatus.

Abstract: Provided herein are methods of producing neutralizing monoclonal antibodies, by cyclical immunization, that cross-react with strains of Influenza virus of the same subtype or different subtypes. Also provided herein are compositions comprising such antibodies and methods of using such antibodies to diagnose, prevent or treat Influenza virus disease.

Abstract: Described herein are compounds of formula (I) or pharmaceutical acceptable salts or solvates thereof, wherein L1, R1, R2, R3, R4, R5, and m are defined in the description. Methods of making said compounds, and compositions containing said compounds which are useful for inhibiting kinases such as IGF-1R are also disclosed.

Abstract: Disclosed are compounds which inhibit the activity of anti-apoptotic Bcl-2 proteins, compositions containing the compounds and methods of treating diseases during which is expressed anti-apoptotic Bcl-2 protein.

Abstract: Described herein are compounds of formula (I) or pharmaceutical acceptable salts or solvates thereof, wherein G1, L1, R2, R3, n, p, Ar1, and Ar2 are defined in the description. Methods of making said compounds, and compositions comprising said compounds which are useful for inhibiting kinases such as IGF-1R are also disclosed.

Abstract: The present invention relates to compounds of formula (I) or pharmaceutical acceptable salts or solvates thereof, wherein G1, R2, R3, R4, R5, n, p, q, Ar1, and Ar2 are defined in the description. The present invention relates also to methods of making said compounds, and compositions comprising said compounds which are useful for inhibiting kinases such as IGF-1R.

Abstract: Disclosed are compounds which inhibit the activity of anti-apoptotic Bcl-2 proteins, compositions containing the compounds and methods of treating diseases during which is expressed anti-apoptotic Bcl-2 protein.

Abstract: Disclosed are compounds which inhibit the activity of anti-apoptotic Bcl-2 or Bcl-xL proteins, compositions containing the compounds and methods of treating diseases during which are expressed anti-apoptotic Bcl-2 protein.

Abstract: A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system.

Abstract: A system and method are provided for delaying a signal communicated from a system to a plurality of memory circuits. Included is a component in communication with a plurality of memory circuits and a system. Such component is operable to receive a signal from the system and communicate the signal to at least one of the memory circuits after a delay. In other embodiments, the component is operable to receive a signal from at least one of the memory circuits and communicate the signal to the system after a delay.

Abstract: An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc.

Abstract: A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.

Abstract: A method and apparatus for compacting test responses containing unknown values in a scan-based integrated circuit. The proposed X-driven compactor comprises a chain-switching matrix block and a space compaction logic block. The chain-switching matrix block switches the internal scan chain outputs before feeding them to the space compaction logic block for compaction so as to minimize X-induced masking and error masking. The X-driven compactor further selectively includes a finite-memory compaction logic block to further compact the outputs of the space compaction logic block.

Abstract: Compounds of formula (25) that inhibit protein kinases, compositions containing the compounds and methods of treating diseases using the compounds are disclosed.