Abstract: In one embodiment, a method for processing, at an enhanced Session Initiation Protocol (SIP) proxy (e-proxy), (1) a SIP INVITE message to a first user at an IPv4/IPv6 dual-stack (DS) host, connected to an IPv6 network, from a second user at an IPv4 host, connected to an IPv4 network. The e-proxy receives the SIP INVITE message from the IPv4 network. When the e-proxy determines that Dual Stack Transition Mechanism (DSTM) service is required, the e-proxy obtains a temporary IPv4 address for the DS host, finds a suitable tunnel end-point (TEP), and sends a corresponding, but modified, INVITE message to the DS host. The modified INVITE message body includes invocation of DSTM service, the temporary IPv4 address, the TEP's IPv6 address, and the IPv4 host's IPv4 address. The e-proxy sends a BIND message to the TEP to bind the DS host's IPv6 address to the temporary IPv4 address for proper tunneling.

Abstract: A pipelined scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. A decompressor is embedded between N scan chains and M scan chains, where N<M, to broadcast compressed scan data patterns driven through the N scan chains into decompressed scan data patterns stored in the M scan chains. To speed up the shift-in/shift-out operation during decompression, the decompressor can be further split into two or more pipelined decompressors each placed between two sets of intermediate scan chains. The invention further comprises one or more pipelined compressors to speed up the shift-in/shift-out operation during compression.

Abstract: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of physical memory circuits and a system. The interface circuit is operable to interface the physical memory circuits and the system for simulating at least one virtual memory circuit with a first power behavior that is different from a second power behavior of the physical memory circuits.

Abstract: One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory-related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.

Abstract: A power saving system and method are provided. In use, at least one of a plurality of memory circuits is identified that is not currently being accessed. In response to the identification of the at least one memory circuit, a power saving operation is initiated in association with the at least one memory circuit.

Abstract: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing a power management operation in association with at least a portion of the memory circuits. Such power management operation is performed during a latency associated with one or more commands directed to at least a portion of the memory circuits.

Abstract: A method comprising forming a first dielectric layer over an electrode formed to a first contact point on a substrate, the electrode having a contact area; patterning the first dielectric layer into a body, a thickness of the first dielectric layer defining a side wall; forming at least one spacer along the side wall of the first dielectric body, the at least one spacer overlying a portion of the contact area; forming a second dielectric layer on the contact area; removing the at least one spacer; and forming a material comprising a second contact point to the contact area. An apparatus comprising a volume of programmable material; a conductor; and an electrode disposed between the volume of programmable material and the conductor, the electrode having a contact area coupled to the volume of programmable material.

Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.

Abstract: The present invention comprises an apparatus and a method for mass analyses of an array of samples contained in distinct sample holders. The sample holders are placed on a plurality of sensors which preferably comprise an array of microbalances providing output signals comprising mass data on the array of samples.

Abstract: The present invention comprises an apparatus and a method for mass analyses of an array of samples contained in distinct sample holders. The sample holders are placed on a plurality of sensors which preferably comprise an array of microbalances providing output signals comprising mass data on the array of samples.

Abstract: A method of harvesting vibrational energy is provided. This method involves generating a high magnetic flux density field within a current induction conductor such as an induction coil. The high magnetic flux density field is generated between two same pole magnets. The high magnetic flux density field may be displaced relative to the current induction conductor with vibrational energy. These displacements then cause the current induction conductor to be energized. The two same pole magnets are mounted between piezoelectric transducer (PZT) materials. These PZT materials generate an electric potential when the PZT materials are subject to the mechanical stresses of the vibrational energy. The electrical energy translated from the vibrational energy through both the energized current induction conductor and stress PZT materials may then be used to power a power circuitry or be stored for later use.

Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.

Abstract: A method and pump that accurately senses air in a fluid delivery line pulses or activates and deactivates the air sensor(s) multiple times during the pumping phase of the fluid delivery cycle and can generate alarms based upon a single indication or a cumulative indication of air in the line. The pump can include multiple air sensors spaced along the delivery line so that the method can use the multiple signals therefrom to distinguish real moving air bubbles from false positives and/or air bubbles adhered to the inner wall of the line.

Abstract: Compounds having methionine aminopeptidase-2 inhibitory (MetAP2) are described. Also described are pharmaceutical compositions comprising the compounds, methods of treatment using the compounds, methods of inhibiting angiogenesis, and methods of treating cancer.

Abstract: Measurements are taken of moisture, BTU/lb (British Thermal Units per pound), ash, forms of sulfur, volatile material, grindability, and absorption properties of any of a wide variety of mine-run solid fuels. Using that information, a dry electromagnetic process technology has been developed that can be controlled and monitored to selectively alter and enhance metallurgical solid fuel properties. Specific changes include altering the mechanical structure and chemical composition of solid fuels such as coal, coal coke or petroleum coke, increasing the BTU/lb to optimum levels, decreasing all forms of sulfur, and decreasing ash, while maintaining the BTU/lb of the fuels. A new family of solid fuel designer coals not found in nature can be produced via these methods and apparatus.

Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Abstract: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for communicating a first number of power management signals to at least a portion of the memory circuits that is different from a second number of power management signals received from the system.

Abstract: The present disclosure is directed to stretch or elastic textile articles having wrinkle resistance. The textile articles are preferably cellulosic, more preferably cotton-based. The stretch levels for these articles is preferably greater than about 8 percent and preferably have a DP rating (as determined according to AATCC 143-1996 or AATCC 124-2001) of at least 3.0.

Abstract: A method for improving Mg doping of Group III-N materials grown by MOCVD preventing condensation in the gas phase or on reactor surfaces of adducts of magnesocene and ammonia by suitably heating reactor surfaces between the location of mixing of the magnesocene and ammonia reactants and the Group III-nitride surface whereon growth is to occur.