Patents by Inventor Ta Ching

Ta Ching has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146205
    Abstract: A flyback power converter includes a power transformer, a first lossless voltage conversion circuit, a first low-dropout linear regulator and a secondary side power supply circuit. The first low-dropout linear regulator (LDO) generates a first operation voltage as power supply for being supplied to a sub-operation circuit. The secondary side power supply circuit includes a second lossless voltage conversion circuit and a second LDO. The second LDO generates a second operation voltage. The first operation voltage and the second operation voltage are shunted to a common node. When a first lossless conversion voltage is greater than a first threshold voltage, the second LDO is enabled to generate the second operation voltage to replace the first operation voltage as power supply supplied to the sub-operation circuit; wherein the second lossless conversion voltage is lower than the first lossless switching voltage.
    Type: Application
    Filed: September 23, 2023
    Publication date: May 2, 2024
    Inventors: Shin-Li Lin, He-Yi Shu, Shih-Jen Yang, Ta-Yung Yang, Yi-Min Shiu, Chih-Ching Lee, Yu-Chieh Hsieh, Chao-Chi Chen
  • Patent number: 11949337
    Abstract: A flyback power converter includes a controller, a high-end driving circuit, an active clamp switch, a main switch and a zero current detection circuit. The high-end driving circuit is coupled to the controller. The active clamp switch is coupled to the high-end driving circuit for driving the active clamp switch. The main switch is coupled to the controller. The zero current detection circuit is coupled to the controller. The main switch and the active clamp switch are arranged on the primary side of a transformer. The switching period of a gate of the active clamp switch and the switching period of a gate of the main switch are controlled in reverse phase to achieve zero voltage or zero current conversion.
    Type: Grant
    Filed: January 9, 2022
    Date of Patent: April 2, 2024
    Assignee: PHIHONG TECHNOLOGY CO., LTD.
    Inventor: Ta-Ching Hsu
  • Patent number: 11929730
    Abstract: An acoustic wave element includes: a substrate; a bonding structure on the substrate; a support layer on the bonding structure; a first electrode including a lower surface on the support layer; a cavity positioned between the support layer and the first electrode and exposing a lower surface of the first electrode; a piezoelectric layer on the first electrode; and a second electrode on the piezoelectric layer, wherein at least one of the first electrode and the second electrode includes a first layer and a second layer that the first layer has a first acoustic impedance and a first electrical impedance, the second layer has a second acoustic impedance and a second electrical impedance, wherein the first acoustic impedance is higher than the second acoustic impedance, and the second electrical impedance is lower than the first electrical impedance.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: March 12, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Ta-Cheng Hsu, Wei-Shou Chen, Chun-Yi Lin, Chung-Jen Chung, Wei-Tsuen Ye, Wei-Ching Guo
  • Patent number: 11923413
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon-Jhy Liaw, Chao-Ching Cheng, Hung-Li Chiang, Shih-Syuan Huang, Tzu-Chiang Chen, I-Sheng Chen, Sai-Hooi Yeong
  • Patent number: 11894238
    Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen, Ru-Gun Liu, Shau-Lin Shue, Tsai-Sheng Gau, Yung-Hsu Wu
  • Publication number: 20230207386
    Abstract: A method of increasing the resistivity of a silicon carbide wafer includes providing a silicon carbide wafer with a first resistivity, and applying a microwave to treat the silicon carbide wafer. The treated silicon carbide wafer has a second resistivity. The second resistivity is higher than the first resistivity. The microwave treated silicon carbide wafer can be applied in a high-frequency device.
    Type: Application
    Filed: December 13, 2022
    Publication date: June 29, 2023
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Mao-Nan CHANG, Ta-Ching HSIAO, Kuo-Lun HUANG, Pei-Ying CHEN
  • Publication number: 20230178120
    Abstract: A method (for recycling charge from a first bit line of a memory device to a second bit line of the memory device) includes: before pre-filling the second bit line, momentarily closing switches to transfer a first charge from the first bit line which is involved in a first read operation to the second bit line which is involved subsequently in a second read operation; and each of the first bit line and the second bit line being served by a same sense amplifier.
    Type: Application
    Filed: February 7, 2023
    Publication date: June 8, 2023
    Inventors: Hung-Chang YU, Ta-Ching YEH
  • Patent number: 11624985
    Abstract: Embodiments of the present disclosure relate to methods for defect inspection. After pattern features are formed in a structure layer, a dummy filling material having dissimilar optical properties from the structure layer is filled in the pattern features. The dissimilar optical properties between materials in the pattern features and the structure layer increase contrast in images captured by an inspection tool, thus increasing the defect capture rate.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: April 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Ching Yu, Shih-Che Wang, Shu-Hao Chang, Yi-Hao Chen, Chen-Yen Kao, Te-Chih Huang, Yuan-Fu Hsu
  • Publication number: 20230098275
    Abstract: A flyback power converter includes a controller, a high-end driving circuit, an active clamp switch, a main switch and a zero current detection circuit. The high-end driving circuit is coupled to the controller. The active clamp switch is coupled to the high-end driving circuit for driving the active clamp switch. The main switch is coupled to the controller. The zero current detection circuit is coupled to the controller. The main switch and the active clamp switch are arranged on the primary side of a transformer. The switching period of a gate of the active clamp switch and the switching period of a gate of the main switch are controlled in reverse phase to achieve zero voltage or zero current conversion.
    Type: Application
    Filed: January 9, 2022
    Publication date: March 30, 2023
    Inventor: Ta-Ching Hsu
  • Patent number: 11587746
    Abstract: A keyboard including a substrate and a key structure is provided. The key structure is disposed on the substrate and includes a keycap, an antenna, and a sensor. The keycap is disposed on the substrate, and a length of the keycap is greater than a width of the keycap. The antenna is disposed on a back surface of the keycap facing toward the substrate. The sensor is disposed below the keycap and is electrically connected with the antenna.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: February 21, 2023
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, Lite-On Technology Corporation
    Inventors: Ta-Ching Lu, Wu-Jeng Li, Chin-Ping Chan, Chih-Jen Kuo
  • Patent number: 11574658
    Abstract: A semiconductor device includes: a sense amplifier; a branched line selectively connectable to the amplifier; an array of bit lines connected to corresponding memory cells; and an intra-sense-amplifier recycling arrangement configured to do as follows including: recovering a first charge from a first bit line associated with a first one of the memory cells, the first charge being associated with a preceding first evaluation performed by the sense amplifier; and boosting the branched line to a reference voltage including reusing the first charge to at least partially charge the branched line; and wherein the sense amplifier is configured to make a second evaluation of a stored value in a second memory cell relative to the reference voltage.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: February 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Chang Yu, Ta-Ching Yeh
  • Patent number: 11541351
    Abstract: A method for removing boron is provided, which includes (a) mixing a carbon source material and a silicon source material in a chamber to form a solid state mixture, (b) heating the solid state mixture to a temperature of 1000° C. to 1600° C., and adjusting the pressure of the chamber to 1 torr to 100 torr. The method also includes (c) conducting a gas mixture of a first carrier gas and water vapor into the chamber to remove boron from the solid state mixture, and (d) conducting a second carrier gas into the chamber.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: January 3, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ta-Ching Hsiao, Chu-Pi Jeng, Kuo-Lun Huang, Mu-Hsi Sung, Keng-Yang Chen, Li-Duan Tsai
  • Publication number: 20220415721
    Abstract: The present disclosure describes a method for controlling radiation conditions and an example system for performing the method. The method includes sending a first setting to configure a radiation device to provide radiation to a substrate undergoing a process operation in a process chamber of the radiation device. The method further includes receiving radiation energy data measured at a plurality of locations of the process chamber and receiving measurement data measured on the substrate during the process operation. The method further includes in response to a variance of the radiation energy data being above a first predetermined threshold and in response to a difference between reference data and the measurement data being above a second predetermined threshold, sending a second setting to configure the radiation device to provide radiation to the substrate.
    Type: Application
    Filed: May 6, 2022
    Publication date: December 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chun TAI, Ta-Ching YANG, Chung-Yi SU, Ping-Cheng LU, Ming-Feng LEE
  • Publication number: 20220344170
    Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.
    Type: Application
    Filed: July 11, 2022
    Publication date: October 27, 2022
    Inventors: Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen, Ru-Gun Liu, Shau-Lin Shue, Tsai-Sheng Gau, Yung-Hsu Wu
  • Patent number: 11415830
    Abstract: An electronic device is provided. The electronic device includes a first substrate, a second substrate, a light-shielding layer, and a color filter layer. The second substrate is disposed opposite to the first substrate. The light-shielding layer is disposed on the second substrate and includes an opening area and a light-shielding area. The color filter layer is disposed on the second substrate and includes a first color filter unit. The first color filter unit includes a first portion and a second portion. In addition, the first portion is at least partially overlapped with the opening area, the second portion is overlapped with the light-shielding area, and there is a first gap between the first portion and the second portion.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: August 16, 2022
    Assignee: INNOLUX CORPORATION
    Inventors: Chen-Kuan Kao, Ta-Ching Chen, Wei-Ming Kao, Chih-Chang Hou
  • Patent number: 11387113
    Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen, Ru-Gun Liu, Shau-Lin Shue, Tsai-Sheng Gau, Yung-Hsu Wu
  • Publication number: 20220189716
    Abstract: The disclosure provides a key structure, including a first electrode, a key cap, and a restoration member. The key cap is disposed on the first electrode. The restoration member is disposed between the key cap and the first electrode. The key cap or the restoration member has a second electrode. A sensing signal is generated by the second electrode with the key cap or the restoration member moving relative to the first electrode.
    Type: Application
    Filed: December 15, 2021
    Publication date: June 16, 2022
    Applicant: Lite-On Technology Corporation
    Inventors: Chun-Chieh Huang, Ming-Fu Yen, Che Hung Wu, Juo-Tau Lee, Ta-Ching Lu, Chieh-Liang Hsiao, Wei-Pin Chuang
  • Publication number: 20210295881
    Abstract: A semiconductor device includes: a sense amplifier; a branched line selectively connectable to the amplifier; an array of bit lines connected to corresponding memory cells; and an intra-sense-amplifier recycling arrangement configured to do as follows including: recovering a first charge from a first bit line associated with a first one of the memory cells, the first charge being associated with a preceding first evaluation performed by the sense amplifier; and boosting the branched line to a reference voltage including reusing the first charge to at least partially charge the branched line; and wherein the sense amplifier is configured to make a second evaluation of a stored value in a second memory cell relative to the reference voltage.
    Type: Application
    Filed: June 8, 2021
    Publication date: September 23, 2021
    Inventors: Hung-Chang YU, Ta-Ching YEH
  • Publication number: 20210275965
    Abstract: A method for removing boron is provided, which includes (a) mixing a carbon source material and a silicon source material in a chamber to form a solid state mixture, (b) heating the solid state mixture to a temperature of 1000° C. to 1600° C., and adjusting the pressure of the chamber to 1 torr to 100 torr. The method also includes (c) conducting a gas mixture of a first carrier gas and water vapor into the chamber to remove boron from the solid state mixture, and (d) conducting a second carrier gas into the chamber.
    Type: Application
    Filed: May 21, 2021
    Publication date: September 9, 2021
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ta-Ching HSIAO, Chu-Pi JENG, Kuo-Lun HUANG, Mu-Hsi SUNG, Keng-Yang CHEN, Li-Duan TSAI
  • Patent number: D956376
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: June 28, 2022
    Assignee: GOLDEEP LTD.
    Inventor: Ta-Ching Chao