Abstract: A semiconductor device, a semiconductor chip and manufacturing methods thereof are provided. The semiconductor device includes: channel structures, vertically spaced apart from one another; a gate structure, intersecting the channel structures and wrapping around each of the channel structures; source/drain structures, in lateral contact with the channel structures from opposite sides of the channel structures; and protection structures, separately disposed along a bottom surface of the gate structure, wherein the channel structures are located between the protection structures, and the protection structures comprise a semiconductor material.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes an isolation structure formed over a substrate, and first nanostructures formed over an isolation structure along a first direction. The semiconductor includes second nanostructures adjacent to the first nanostructure along the first direction. The semiconductor also includes a dielectric wall between the first nanostructures and the second nanostructures, and the dielectric wall includes a low-k dielectric material. The dielectric wall is in direct contact with the first nanostructures and the second nanostructures, and a top surface of the dielectric wall is higher than a top surface of the isolation structure. The semiconductor includes a gate structure formed over the first nanostructures along a second direction, and a cutting structure formed over the dielectric wall. The gate structure is divided into two portions by the cutting structure.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, semiconductor nanosheets vertically stacked upon one another and disposed above the semiconductor substrate, a gate structure surrounding each of the semiconductor nanosheets, inner spacers laterally covering the gate structure and interposed between the semiconductor nanosheets, and source/drain (S/D) regions disposed over the semiconductor substrate and laterally abutting the semiconductor nanosheets. The semiconductor nanosheets serve as channel regions. A bottommost inner spacer of the inner spacers underlying a bottommost semiconductor nanosheet of the semiconductor nanosheets is thinner than a topmost inner spacer of the inner spacers underlying a topmost semiconductor nanosheet of the semiconductor nanosheets. The S/D regions are separated from the gate structure through the inner spacers.

Abstract: Transistors of different types of electronic devices on the same semiconductor substrate are configured with different transistor attributes to increase the performance of the different types of electronic devices. Fin height, shallow source drain (SSD) height, source or drain width, and/or one or more other transistor attributes may be co-optimized for the different types of electronic devices by various semiconductor manufacturing processes such as etching, lithography, process loading, and/or masking, among other examples. This enables the performance of a plurality of types of electronic devices on the same semiconductor substrate to be increased.

Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a source/drain feature over a substrate; a metal gate structure extending lengthwise along a first direction and adjacent to the source/drain feature; a gate isolation structure extending lengthwise along a second direction substantially perpendicular to the first direction, and a source/drain contact electrically coupled to the source/drain feature and including a first portion directly above the source/drain feature and a second portion extending from the first portion along the first direction. In embodiments, the gate isolation structure divides the metal gate structure into two isolated portions. In embodiments, the first portion has a first width along the second direction and the second portion has a second width along the second direction, the first width being greater than the second width.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes semiconductor nanosheets vertically stacked upon one another and disposed above a semiconductor substrate, a gate structure surrounding each of the semiconductor nanosheets, and source/drain regions disposed over the semiconductor substrate and laterally abutting the semiconductor nanosheets. The semiconductor nanosheets serve as channel regions, and a topmost semiconductor nanosheet most distanced from the semiconductor substrate is thinner than an underlying semiconductor nanosheet between the topmost semiconductor nanosheet and the semiconductor substrate.

Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming, over a substrate, a stack extending along a first lateral direction, wherein the stack includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately arranged on top of one another; overlaying a first portion of the stack with a first gate structure, wherein the first gate structure extends along a second lateral direction perpendicular to the first lateral direction; removing a second portion of the stack through a first etching process, wherein the second portion was disposed next to the first portion along the first lateral direction; and removing a third portion of the stack through a second etching process, wherein the third portion was disposed next to a lower part of the second portion.

Abstract: A semiconductor structure includes a substrate, a vertical stack including nanostructures, and a gate structure wrapping around each of the nanostructures. The nanostructures are suspended and vertically arranged over the substrate. The gate structure includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The semiconductor structure further includes inner spacers and gate spacers. The inner spacers are formed on opposite sides of the gate structure, between the nanostructures, and separating the nanostructures from each other. The gate spacers are formed on the opposite sides of the gate structure and over a topmost one of the nanostructures. The gate dielectric layer includes a first portion formed on the nanostructures and a second portion extending from the first portion. The first portion and the second portion have a first thickness and a second thickness, respectively. The first thickness is greater than the second thickness.

Abstract: Semiconductor device structures and methods for manufacturing the same are provided. A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and first nanostructures formed over the isolation structure along a first direction. The semiconductor device structure includes a first gate structure formed over the first nanostructures along a second direction, and a first dielectric structure formed adjacent to the first nanostructures along the first direction. The first dielectric structure is in direct contact with the first nanostructures. The semiconductor device structure includes a second gate structure formed adjacent to the first gate structure, and the second gate structure is formed directly over the first dielectric structure.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes first nanostructures formed over a substrate along a first direction, and second nanostructures formed over the substrate along the first direction. The semiconductor structure includes a first gate structure formed over the first nanostructures and the second nanostructures along a second direction. Each of the first nanostructures has a first width along the second direction, each of the second nanostructures has a second width along the second direction, and the first width is smaller than the second width. The semiconductor structure includes a first base fin structure below the first nanostructures, and the first base fin structure has a first base width. The first base width is greater than the first width.

Abstract: A semiconductor structure includes a first well doped with a first dopant and a second well doped with a second dopant different from the first dopant. From a top view, the first well includes a first base extending lengthwise along a direction, and a first letter-shaped portion and a second letter-shaped portion connected to the first base. From the top view, the second well includes a second base extending lengthwise along the direction and a third letter-shaped portion connected to the second base. The third letter-shaped portion extends into the first well and is keyed to the first letter-shaped portion and the second letter-shaped portion.

Abstract: The present disclosure provides a method that includes providing a workpiece having a semiconductor substrate that includes a first circuit area and a second circuit area, forming a first active region in the first circuit area and a second active region on the second circuit area, forming first gate stacks on the first active region and second gate stacks on the second active region, performing a plurality of implantation processes to introduce a doping species to the first active region with a first dosage and to the second active region with a second dosage different from the first dosage, and forming first source/drain features within first source/drain regions of the first active region and second source/drain features within second source/drain regions of the second active region.

Abstract: A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device formed over a substrate, and the first device comprises a first channel structure. The semiconductor device structure includes a first gate stack wrapped around the first channel structure, and a second device formed over the first device. The second device comprises a plurality of second nanostructures stacked in a vertical direction. The semiconductor device structure include a second gate stack wrapped around the second nanostructures, and a portion of the first gate stack is higher than a topmost second nanostructure.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes first semiconductor channel layers, second semiconductor channel layers, a dielectric wall, a gate structure, a source/drain electrode and an inner spacer. The first semiconductor channel layers are stacked vertically apart along a first direction over a substrate. The second semiconductor channel layers are stacked vertically apart along the first direction over the substrate. The dielectric wall is disposed between and separates the first semiconductor channel layers and the second first semiconductor channel layers, wherein the dielectric wall comprises a liner and a dielectric wall material disposed over the liner. The gate structure extends along a second direction perpendicular to the first direction disposed crossing over a channel region of the first fin structure and a channel region of the second fin structure. The source/drain electrode is in contact with the first semiconductor channel layers.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes first channel layers formed over a substrate along a first direction, and second channel layers adjacent to the first channel layers and over the substrate. The semiconductor structure includes a first gate structure formed over the first channel layers along a second direction.

Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of semiconductor structures, a source/drain (S/D) region, and a gate stack. The substrate includes an active region extending along a first direction. The semiconductor structures are stacked on the active region. The S/D region abuts the plurality of semiconductor structures. The gate stack wraps the semiconductor structures and extends along a second direction different from the first direction. A bottommost semiconductor structure of the semiconductor structures has a width in the second direction greater than a width of a topmost semiconductor structure of the semiconductor structures in the second direction.

Abstract: A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, an S/D feature disposed over the semiconductor fin, and a first dielectric fin and a second dielectric fin disposed over the substrate, where the semiconductor fin is disposed between the first dielectric fin and the second dielectric fin, where a first air gap is enclosed by a first sidewall of the epitaxial S/D feature and the first dielectric fin, and where a second air gap is enclosed by a second sidewall of the epitaxial S/D feature and the second dielectric fin.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes first nanostructures formed over a substrate along a first direction, and a first gate structure formed over the first nanostructures along a second direction. The semiconductor structure includes a gate spacer layer formed adjacent to the first gate structure, and a first number of the nanostructures directly below the gate spacer layer is greater than a second number of the nanostructures directly below the first gate structure.