Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a plurality of dummy gates over a substrate and performing a first etch step and a second etch step on the substrate exposed between the dummy gates. The first etch step includes an anisotropic etching process and an isotropic etching process. The second includes an isotropic etching step.

Abstract: Embodiments provide a method for forming a semiconductor device structure, includes forming a fin structure having first semiconductor layers and second semiconductor layers alternatingly stacked thereover, forming a sacrificial gate structure over a portion of the fin structure, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers to expose portions of each of the first semiconductor layers. The method includes surrounding the exposed portions of each of the first semiconductor layers with a cladding layer, wherein the cladding layer is formed of a material chemically different from the first semiconductor layers, and the cladding layer has a first atomic percentage of germanium.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a gate structure formed over a substrate, and a first source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes an S/D contact structure formed over the first S/D structure, and a dielectric wall formed below the gate structure and the S/D contact structure. The dielectric wall has a first portion directly below the S/D contact structure and a second portion directly below the gate structure, the first portion has a first height along a vertical direction, the second portion has a second height along the vertical direction, and the first height is smaller than the second height.

Abstract: A method includes forming a semiconductor fin over a substrate; forming isolation structures laterally surrounding the semiconductor fin; forming a gate structure over the semiconductor fin; forming a first spacer layer and a second spacer layer over the gate structure and the semiconductor fin; etching back the second spacer layer, such that a top surface of the second spacer layer is lower than a top surface of the first spacer layer; after etching back the second spacer layer, forming a third spacer layer over the first spacer layer and the second spacer layer; etching the first, second, and third spacer layers and the semiconductor fin to form recesses; and forming epitaxial source/drain structures in the recesses.

Abstract: Transistors of different types of electronic devices on the same semiconductor substrate are configured with different transistor attributes to increase the performance of the different types of electronic devices. Fin height, shallow source drain (SSD) height, source or drain width, and/or one or more other transistor attributes may be co-optimized for the different types of electronic devices by various semiconductor manufacturing processes such as etching, lithography, process loading, and/or masking, among other examples. This enables the performance of a plurality of types of electronic devices on the same semiconductor substrate to be increased.

Abstract: Structures and methods for the co-optimization of various device types include performing a first photolithography and etch process to simultaneously form a first source/drain recess for a first device in a first substrate region and a third source/drain recess for a third device in a third substrate region different than the first substrate region. In some embodiments, the method further includes performing a second photolithography and etch process to form a second source/drain recess for a second device in a second substrate region different than the first and third substrate regions. The method further includes forming a first source/drain feature within the first source/drain recess, a second source/drain feature within the second source/drain recess, and a third source/drain feature within the third source/drain recess.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present disclosure includes an active region having a channel region and a source/drain region, a gate structure over the channel region, a gate spacer layer disposed over the channel region and extending along a sidewall of the gate structure, an epitaxial source/drain feature over the source/drain region, a contact etch stop layer (CESL) disposed on the epitaxial source/drain feature and extending along a sidewall of the gate spacer layer, a source/drain contact disposed over the epitaxial source/drain feature, and a dielectric cap layer disposed over the gate structure, the gate spacer layer and at least a portion of the CESL. A sidewall of the source/drain contact is in direct contact with a sidewall of the CESL.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming first and second semiconductor fins; forming first and second gate structures respectively over first regions of the first and second semiconductor fins; forming a first dummy spacer at a sidewall of the first gate structure adjacent a second region of the first semiconductor fin; etching a first source/drain recess in the second region of the first semiconductor fin; forming a n-type source/drain epitaxial structure in the first source/drain recess; forming a second dummy spacer at a sidewall of the second gate structure adjacent a second region of the second semiconductor fin, wherein the second dummy spacer has a thickness less than that of the first dummy spacer; etching a second source/drain recess in the second region of the second semiconductor fin; and forming a p-type source/drain epitaxial structure in the second source/drain recess.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor structure includes a substrate, a first active region, a second active region and a third active region over the substrate, a first gate structure over a channel region of the first active region, a second gate structure over a channel region of the second active region, a third gate structure over a channel region of the third active region, a first cap layer over the first gate structure, a second cap layer over the second gate structure, and a third cap layer over the third gate structure. A height of the second gate structure is smaller than a height of the first gate structure or a height of the third gate structure.

Abstract: Structures and formation methods of a semiconductor device are provided. The method includes forming a first dummy gate structure across a first fin in a first transistor region of a semiconductor substrate and a second dummy gate structure across a second fin in a second transistor region of the semiconductor substrate. The method also includes selectively introducing atomic or ionic species into the second fin on opposite sides of the second dummy gate structure and etching portions of the first and second fins, so as to form first and second recesses. Each recess is in the respective fin on a side of the respective dummy gate structure. The first recess has a different depth than the second recess. The method further includes forming first and second source/drain features in the first and second recesses, respectively.

Abstract: A semiconductor device includes a substrate having a first region and a second region. Multiple nanostructures are vertically stacked above the first region of the substrate. A first gate dielectric layer wraps each of the nanostructures. A first gate electrode layer is disposed on the first gate dielectric layer. A fin protruding from the second region of the substrate. The fin includes alternating first and second semiconductor layers with different material compositions. A second gate dielectric layer is disposed on top and sidewall surfaces of the fin. A second gate electrode layer is disposed on the second gate dielectric layer. A thickness of the first gate dielectric layer is smaller than a thickness of the second gate dielectric layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base, a first fin, and a second fin over the base. The method includes forming a gate stack over the first fin and the second fin. The method includes forming a first spacer over gate sidewalls of the gate stack and a second spacer adjacent to the second fin. The method includes partially removing the first fin and the second fin. The method includes forming a first source/drain structure and a second source/drain structure in the first trench and the second trench respectively. A first ratio of a first height of the first merged portion to a second height of a first top surface of the first source/drain structure is greater than or equal to about 0.5.

Abstract: A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.

Abstract: A semiconductor structure includes a first semiconductor device formed over a substrate. The first semiconductor device includes a first source/drain feature over the substrate, a first gate structure over the substrate, a first conductive feature over the first source/drain feature, and a first insulation layer between the first gate structure and the first conductive feature, wherein the first insulation layer comprises a first contact etching stop layer (CESL) in contact with the first source/drain feature.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate including a first well region of a first conductivity type. The semiconductor device structure also includes a first fin structure and an adjacent second fin structure formed in and protruding from the first well region. The semiconductor device structure also includes a first isolation structure formed in the first well region between the first fin structure and the second fin structure. A first sidewall surface of the first fin structure faces to a second sidewall surface of the second fin structure. The first sidewall surface and the second sidewall surface each extend along at least two directions from a bottom of the first isolation structure to a top of the first isolation structure.

Abstract: Transistors of different types of electronic devices on the same semiconductor substrate are configured with different transistor attributes to increase the performance of the different types of electronic devices. Fin height, shallow source drain (SSD) height, source or drain width, and/or one or more other transistor attributes may be co-optimized for the different types of electronic devices by various semiconductor manufacturing processes such as etching, lithography, process loading, and/or masking, among other examples. This enables the performance of a plurality of types of electronic devices on the same semiconductor substrate to be increased.

Abstract: A semiconductor structure includes a first active region over a substrate and extending along a first direction, a gate structure over the first active region and extending along a second direction substantially perpendicular to the first direction, a gate-cut feature abutting an end of the gate structure, and a channel isolation feature extending along the second direction and between the first active region and a second active region. The gate structure includes a metal electrode in direct contact with the gate-cut feature. The channel isolation feature includes a liner on sidewalls extending along the second direction and a dielectric fill layer between the sidewalls. The gate-cut feature abuts an end of the channel isolation feature and the dielectric fill layer is in direct contact with the gate-cut feature.

Abstract: A structure includes a fin on a substrate; first and second gate stacks over the fin and including first and second gate dielectric layers and first and second gate electrodes respectively; and a dielectric gate over the fin and between the first and second gate stacks. The dielectric gate includes a dielectric material layer on a third gate dielectric layer. In a cross-sectional view cut along a direction parallel to a lengthwise direction of the fin and offset from the fin, the first gate dielectric layer forms a first U shape, the third gate dielectric layer forms a second U shape, a portion of the first gate electrode is disposed within the first U shape, a portion of the dielectric material layer is disposed within the second U shape, and a portion of an interlayer dielectric layer is disposed laterally between the first and the second U shapes.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The method includes forming a spacer structure over a sidewall of the gate stack. The method includes forming a source/drain structure in and over the substrate, wherein a portion of the spacer structure is between the source/drain structure and the gate stack. The method includes partially removing the outer layer, wherein a first lower portion of the outer layer remains between the source/drain structure and the gate stack. The method includes partially removing the middle layer, wherein a second lower portion of the middle layer remains between the source/drain structure and the gate stack.

Abstract: Methods and structures for the co-optimization of memory and logic devices. A device includes a substrate having a first region and a second region. The device may include a first gate structure disposed in the first region and a second gate structure disposed in the second region. The device may further include a first source/drain feature disposed adjacent to the first gate structure and a second source/drain feature disposed adjacent to the second gate structure. A first top surface of the first source/drain feature and a second top surface of the second source/drain feature are substantially level. A first bottom surface of the first source/drain feature is a first distance away from the first top surface, and a second bottom surface of the second source/drain feature is a second distance away from the second top surface. In some cases, the second distance is greater than the first distance.