Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.

Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming a first fin structure with a first composition and a second fin structure with a second composition, oxidizing the first fin structure to form a first oxide layer and oxidizing the second fin structure to form a second oxide layer, removing the second oxide layer formed on the second fin structure, oxidizing the second fin structure to form a third oxide layer over the second fin structure, and forming a first metal gate electrode layer over the first oxide layer and a second metal gate electrode layer over the third oxide layer.

Abstract: A method includes depositing a semiconductor stack within a first region and a second region on a substrate, the semiconductor stack having alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes removing a portion of the semiconductor stack from the second region to form a trench and with an epitaxial growth process, filling the trench with the second type of semiconductor material.

Abstract: A use of an anthranilic acid derivative as a matrix for a MALDI Mass spectrometry, comprising: preparing a matrix compound represented by the following formula: wherein X is selected from hydrogen and a hydroxyl group, and Y is selected from hydrogen, a methyl group or an acetyl group, provided that when X is hydrogen, Y is hydrogen or an acetyl group, and when X is a hydroxyl group, Y is a methyl group; applying the matrix compound and an analyte onto a sample holder; and analyzing the analyte by the MALDI mass spectrometer.

Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to an embodiment includes a first cell disposed over a first well doped with a first-type dopant, a second cell disposed over the first well, and a tap cell disposed over a second well doped with a second-type dopant different from the first-type dopant. The tap cell is sandwiched between the first cell and the second cell. The first cell includes a first plurality of transistors and the second cell includes a second plurality of transistors.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a nanostructure disposed over a substrate, wherein the nanostructure includes a plurality of semiconductor layers separated vertically from each other and a dummy pattern layer including dielectric material disposed over and separated vertically from a top semiconductor layer of the plurality of semiconductor layers. The exemplary semiconductor device also comprises a gate structure disposed over a channel region, wherein the gate structure wraps around each of the plurality of semiconductor layers and the dummy pattern layer of the nanostructure.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming first and second well regions with different conductivity types in a semiconductor substrate. A well interface is formed between the first and second well regions. The method also includes patterning the semiconductor substrate to form a first fin structure in the first well region, a second fin structure in the second well region, and a first trench between the first and second fin structures. The first trench exposes the well interface in the semiconductor substrate. The method further includes forming insulating spacers on opposite sidewalls of the first trench and etching the semiconductor substrate below the first trench using the insulating spacers as an etch mask, to form a second trench below the first trench. In addition, the method includes filling the first and second trenches with an insulating material.

Abstract: A semiconductor structure includes a first active region over a substrate and extending along a first direction, a gate structure over the first active region and extending along a second direction substantially perpendicular to the first direction, a gate-cut feature abutting an end of the gate structure, and a channel isolation feature extending along the second direction and between the first active region and a second active region. The gate structure includes a metal electrode in direct contact with the gate-cut feature. The channel isolation feature includes a liner on sidewalls extending along the second direction and a dielectric fill layer between the sidewalls. The gate-cut feature abuts an end of the channel isolation feature and the dielectric fill layer is in direct contact with the gate-cut feature.

Abstract: A semiconductor structure includes a first active region over a substrate and extending along a first direction, a gate structure over the first active region and extending along a second direction substantially perpendicular to the first direction, a gate-cut feature abutting an end of the gate structure, and a channel isolation feature extending along the second direction and between the first active region and a second active region. The gate structure includes a metal electrode in direct contact with the gate-cut feature. The channel isolation feature includes a liner on sidewalls extending along the second direction and a dielectric fill layer between the sidewalls. The gate-cut feature abuts an end of the channel isolation feature and the dielectric fill layer is in direct contact with the gate-cut feature.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate including a first well region and a second well region that have different conductivity types and are adjacent to each other. A first fin structure protrudes from the semiconductor substrate and is formed in the first well region. A second fin structure protrudes from the semiconductor substrate and is formed in the second well region and adjacent to the first fin structure. A first multi-step isolation structure that includes a first isolation portion is formed between the first fin structure and the second fin structure. A second isolation portion extends from the bottom surface of the first isolation portion. The second isolation portion has a top width that is narrower than the bottom width of the first isolation portion.

Abstract: Methods for forming semiconductor structures are provided. The method includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate and patterning the first semiconductor layers and the second semiconductor layers to form a first fin structure. The method further includes forming a first trench in the first fin structure and forming a first source/drain structure in the first trench. The method further includes partially removing the first source/drain structure to form a second trench in the first source/drain structure and forming a first contact in the second trench.

Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.

Abstract: A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.

Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.

Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate including a first well region and a second well region that have different conductivity types and are adjacent to each other. A first fin structure protrudes from the semiconductor substrate and is formed in the first well region. A second fin structure protrudes from the semiconductor substrate and is formed in the second well region and adjacent to the first fin structure. A first multi-step isolation structure that includes a first isolation portion is formed between the first fin structure and the second fin structure. A second isolation portion extends from the bottom surface of the first isolation portion. The second isolation portion has a top width that is narrower than the bottom width of the first isolation portion.

Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.

Abstract: A semiconductor device includes a substrate, first and second source/drain features, and a dielectric plug. The substrate has a semiconductor fin. The first and second source/drain features are over first and second portions of the semiconductor fin, respectively. The dielectric plug is at least partially embedded in a third portion of the semiconductor fin. The third portion is in between the first and second portions of the semiconductor fin. The dielectric plug includes a first dielectric material and a second dielectric material different from the first dielectric material.

Abstract: A method for manufacturing an image sensor with deep trench spacing isolation is provided. A trench is formed in a semiconductor substrate, around and between a plurality of pixel regions of the semiconductor substrate. A cap is formed using epitaxy to seal a gap between sidewalls of the trench. Pixel sensors corresponding to the plurality of pixel regions are formed over or within the corresponding pixel regions. An image sensor resulting from the method is also provided.

Abstract: A charging equipment including a charging module, a communicating module, and a control module. The charging module is configured to charge a device for charging according to a control signal and produce a detecting signal according to a magnitude of an output current of the charging module. The communicating module has a communicating range. The communicating module selectively outputs the detecting signal produced by the charging module to another charging equipment operating in the same communicating range, or selectively receives a detecting signal produced by another charging equipment operating in the same communicating range. The control module electrically connects to the communicating module.