Abstract: A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.

Abstract: A method for making a semiconductor device includes providing a substrate of a first conductivity type and having a surface region, forming a well region of a second conductivity type and having a first depth in the substrate, adding a gate dielectric layer overlying the surface region, adding a gate layer overlying the gate dielectric layer, forming a first LDD region of the first conductivity type and having a second depth within the well region, forming an emitter region of the second conductivity type within the first LDD region, and forming a second LDD region of the first conductivity type with the well region, a channel region separates the first and second LDD regions. The method further includes forming a source region being of the first conductivity type within the second LDD region and adding an output pad coupled to both the drain and emitter regions.

Abstract: An ESD device includes a first and second well regions disposed in a semiconductor substrate. The first well region comprises a plurality of N wells spaced at a predetermined length. A heavily doped P+ region and a heavily doped N+ region are disposed in each of the N wells. The heavily doped N+ region is coupled to Vdd and a heavily doped P+ region in an N well is electrically coupled to the heavily doped N+ region in an adjacent N well. The second well region comprises a P well abutting an N well. A heavily doped P+ region and a heavily doped N+ region are disposed in the P well. The heavily doped N+ region in the P well is electrically coupled to the heavily doped P+ region of the adjacent N well in common with an I/O circuit, and the heavily doped P+ region is coupled to Vss.

Abstract: A method for making a semiconductor device includes providing a substrate of a first conductivity type and having a surface region, forming a well region of a second conductivity type and having a first depth in the substrate, adding a gate dielectric layer overlying the surface region, adding a gate layer overlying the gate dielectric layer, forming a first LDD region of the first conductivity type and having a second depth within the well region, forming an emitter region of the second conductivity type within the first LDD region, and forming a second LDD region of the first conductivity type with the well region, a channel region separates the first and second LDD regions. The method further includes forming a source region being of the first conductivity type within the second LDD region and adding an output pad coupled to both the drain and emitter regions.

Abstract: An ESD device includes a first and second well regions disposed in a semiconductor substrate. The first well region comprises a plurality of N wells spaced at a predetermined length. A heavily doped P+ region and a heavily doped N+ region are disposed in each of the N wells. The heavily doped N+ region is coupled to Vdd and a heavily doped P+ region in an N well is electrically coupled to the heavily doped N+ region in an adjacent N well. The second well region comprises a P well abutting an N well. A heavily doped P+ region and a heavily doped N+ region are disposed in the P well. The heavily doped N+ region in the P well is electrically coupled to the heavily doped P+ region of the adjacent N well in common with an I/O circuit, and the heavily doped P+ region is coupled to Vss.

Abstract: A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.

Abstract: A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.

Abstract: A design for a wide input common mode voltage comparator is provided which reduces the delay between outputs from component comparators. The wide input common mode voltage comparator includes a first comparator configured to receive a differential input. The first comparator is further configured to accommodate high common mode voltages. The wide input common mode voltage comparator further includes a second comparator configured to receive the differential input. The first comparator is further configured to accommodate low common mode voltages. Additionally, the threshold voltages of the active devices within the comparator are between ?100 to 100 mV. Furthermore, the wide input common mode voltage comparator includes a summing circuit configured to receive the outputs of the first and second comparators to create a single-ended output.

Abstract: System and method for providing live insertion. According to an embodiment, the present invention provides an integrated circuit. The integrated circuit includes a first port configured to be electrically coupled to a pad. The first port includes a first connection, a second connection, and a third connection. The integrated circuit also includes a first resistor having a first terminal and a second terminal. Additionally, the integrated circuit includes a second resistor having a third terminal and a forth terminal. The integrated circuit additionally includes a voltage source configured to provided a first voltage. The integrated circuit further includes a first PMOS transistor having a first gate terminal, a first drain terminal and a first source terminal. In addition, the integrated circuit includes a second PMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal.

Abstract: A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.

Abstract: System and method for providing live insertion. According to an embodiment, the present invention provides an integrated circuit. The integrated circuit includes a first port configured to be electrically coupled to a pad. The first port includes a first connection, a second connection, and a third connection. The integrated circuit also includes a first resistor having a first terminal and a second terminal. Additionally, the integrated circuit includes a second resistor having a third terminal and a forth terminal. The integrated circuit additionally includes a voltage source configured to provided a first voltage. The integrated circuit further includes a first PMOS transistor having a first gate terminal, a first drain terminal and a first source terminal. In addition, the integrated circuit includes a second PMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal.

Abstract: A system and method for controlling an input/output driver. The system includes a control system configured to receive a first supply voltage and a second supply voltage and generate a control signal, and a first transistor including a first gate, a first terminal, and a second terminal. The first gate is configured to receive the control signal, and the first terminal is configured to receive the first supply voltage. Additionally, the system includes a second transistor including a second gate, a third terminal, and a fourth terminal, and the second gate is coupled to the second terminal. Moreover, the system includes a third transistor including a third gate, a fifth terminal, and a sixth terminal, and the third gate is configured to receive the control signal. Also, the system includes an input/output pad coupled to the fourth terminal and the fifth terminal.

Abstract: A system and method for controlling an input/output driver. The system includes a control system configured to receive a first supply voltage and a second supply voltage and generate a control signal, and a first transistor including a first gate, a first terminal, and a second terminal. The first gate is configured to receive the control signal, and the first terminal is configured to receive the first supply voltage. Additionally, the system includes a second transistor including a second gate, a third terminal, and a fourth terminal, and the second gate is coupled to the second terminal. Moreover, the system includes a third transistor including a third gate, a fifth terminal, and a sixth terminal, and the third gate is configured to receive the control signal. Also, the system includes an input/output pad coupled to the fourth terminal and the fifth terminal.

Abstract: A system and method for controlling an input/output driver. The system includes a control system configured to receive a first supply voltage and a second supply voltage and generate a control signal, and a first transistor including a first gate, a first terminal, and a second terminal. The first gate is configured to receive the control signal, and the first terminal is configured to receive the first supply voltage. Additionally, the system includes a second transistor including a second gate, a third terminal, and a fourth terminal, and the second gate is coupled to the second terminal. Moreover, the system includes a third transistor including a third gate, a fifth terminal, and a sixth terminal, and the third gate is configured to receive the control signal. Also, the system includes an input/output pad coupled to the fourth terminal and the fifth terminal.

Abstract: The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in an npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with an unique emitter design layout. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements.

Abstract: A system and method for controlling an input/output driver. The system includes a control system configured to receive a first supply voltage and a second supply voltage and generate a control signal, and a first transistor including a first gate, a first terminal, and a second terminal. The first gate is configured to receive the control signal, and the first terminal is configured to receive the first supply voltage. Additionally, the system includes a second transistor including a second gate, a third terminal, and a fourth terminal, and the second gate is coupled to the second terminal. Moreover, the system includes a third transistor including a third gate, a fifth terminal, and a sixth terminal, and the third gate is configured to receive the control signal. Also, the system includes an input/output pad coupled to the fourth terminal and the fifth terminal.

Abstract: A novel device structure and process are described for an SCR ESD protection device used with shallow trench isolation structures. The invention incorporates an SCR device with all SCR elements essentially contained within the same active area without STI elements being interposed between the device anode and cathode elements. This enhances ESD performance by eliminating thermal degradation effects caused by interposing STI structures, and enhances the parasitic bipolar characteristics essential to ESD event turn on. Enabling this unique design is the use of an insulation oxide surface feature which prevents the formation of contact salicides in unwanted areas. This design is especially suited to silicon-on-insulator design, as well as conventional SCR and LVTSCR designs.

Abstract: A method to form a SCR device in the manufacture of an integrated circuit device is achieved. The method comprises providing a SOI substrate comprising a silicon layer overlying a buried oxide layer. The silicon layer further comprises a first well of a first type and a second well of a second type. A first heavily doped region of the first type is formed in the second well to form an anode terminal. A second heavily doped region of the second type is formed in the first well to form a cathode terminal and to complete the SCR device. A gate isolation method is described. A salicide method is described. LVT-SCR methods, including a floating-well, LVT-SCR method, are described.

Abstract: The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in an npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with an unique emitter design layout. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements.

Abstract: The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in an npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with an unique emitter design layout. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements.