Abstract: A circuit for controlling a non-volatile memory cell having a source, a drain, a control gate, and a bulk is disclosed. The control circuit comprises a voltage source, a first charge-pumping circuit, a word-line switch, a second charge-pumping circuit, a source switch, a third charge-pumping circuit, and a bulk switch. The first charge-pumping circuit, second charge-pumping circuit and third charge-pumping circuit respectively generate a first positive voltage, second positive voltage and negative voltage in response to the voltage source. The word-line switch selects and applies one of the voltage source or the first positive voltage to the control gate. The source switch selects and applies one of a ground potential or the second positive voltage to the source. The bulk switch selects and applies one of the ground potential or the negative voltage to the bulk.

Abstract: An integrated circuit package includes a semiconductor chip, a plurality of wired pins, and at least one non-wired pin. The size of the non-wired pin is minimized, or the non-wired pin is eliminated, in order to increase the lead pin spacing. The increase in lead pin spacing prevents electrostatic discharge failure in an integrated circuit package due to electrostatic stressing of the non-wired pin.

Abstract: An integrated circuit package includes a semiconductor chip, a plurality of wired pins, and at least one non-wired pin. The size of the non-wired pin is minimized, or the non-wired pin is eliminated, in order to increase the lead pin spacing. The increase in lead pin spacing prevents electrostatic discharge failure in an integrated circuit package due to electrostatic stressing of the non-wired pin.

Abstract: In a multiple-supply CMOS IC, if VDDH is applied slower than VDDL during powering up, some diffusion junctions normally reversed-biased may momentarily become forward-biased and produce latch-up to produce permanent damage to circuits. Therefore a protection circuit against latch-up in a multiple-supply IC is provided. The protection circuit comprises an N-channel MOSFET, which has its gate connected to the high-voltage bus, its drain connected to the low-voltage supply, and its source connected to the low-voltage bus to control the power-up sequence of high voltage and low voltage for the multiple-supply IC and to prevent latch-up. The N-channel MOSFET can be of different modes, such as enhancement mode, depletion mode or enhancement mode having a low threshold voltage.

Abstract: An electrostatic discharge protective circuit of the invention includes a silicon controller rectifier (SCR) and a current diverter. The current diverter is used to bypass an initial low current thereby to prevent the SCR from being triggered by the low current. Thus, a trigger current required to activate the SCR can be greatly increased thereby to maintain an internal circuit at a normal operating state.

Abstract: An electrostatic discharge protection circuit protects an internal circuit that is coupled to a pad from electrostatic discharge damage. The electrostatic discharge protection circuit comprises at least one silicon-controlled rectifier and an erasable programmable read only memory. The silicon-controlled rectifier is configured with an anode and a cathode connected to the pad and a grounding node, respectively. The erasable programmable read only memory is configured with a drain connected to the pad, a source connected to the grounding node, and a control gate connected to the grounding node. Accordingly, the erasable programmable read only memory enters breakdown to be programmed and triggers the silicon-controlled rectifier to conduct a current when electrostatic discharge stress occurs at the pad.

Abstract: An electrostatic discharge protection circuit immune to latch-up during normal operation is disclosed. The ESD protection circuit is positioned at an IC pad for protecting an internal circuit within an integrated circuit from ESD damage. The electrostatic discharge protection circuit comprises a silicon-controlled rectifier and an ON/OFF controller. The silicon-controlled rectifier coupled between the IC pad and a grounding node to form an ESD path, wherein the ON/OFF controller is arranged in the conduction path. During normal operation the ON/OFF controller disconnects the ESD path so as to avoid latch-up even if noise interference happens.

Abstract: A method for fabricating an electrostatic discharge device is disclosed. The method forms successively a gate dielectric layer and a gate electrode over a semiconductor substrate. The gate electrode is then utilized as a mask for a first ion implantation for forming a first lightly-doped region in the substrate. Moreover, a second ion implantation step is carried out, using the gate electrode as a mask, to form a second lightly-doped region under the first lightly-doped region in the substrate. A sidewall spacer is then formed on sidewall of the gate electrode. Finally, using the sidewall spacer and the gate electrode as a mask, a third ion implantation step is carried out to form a heavily-doped region in the substrate.

Abstract: The protection circuit of the invention connects in series with an internal circuit between a first power source and a second power source. The protection circuit includes a switch which is connected with the internal circuit and one of the first power source and a second power source; and a delay circuit which connects with the switch. The switch which is controlled by the delay circuit is closed for providing a voltage to the internal circuit in normal operation mode, and is opened when an electrostatic stress occurs.

Abstract: An ESD event detector in accordance with the present invention is implemented by an amplifier-like structure, an input device of which is constituted by a non-volatile memory transistor. The instantaneous high voltage while an ESD pulse stresses at an integrated circuit pad alters the threshold voltage of the input device. Thereafter, the DC offset of the amplifier-like device is measured to know whether or not an ESD event occurred during the phases of testing, assembly, installation, or operation.

Abstract: The ESD circuit of the present invention comprises a protection device, and output circuitry. The ESD circuitry illustratively comprises an NMOS and PMOS transistor and two protective diodes. However, in place of the NMOS and PMOS transistors, any two-terminal protection device may be used. The protection device of the present invention comprises the diodes of the ESD circuitry. These diodes are formed within the seal-ring structure of an IC. The seal-ring structure is formed using the following steps. First, a field oxide is grown. N.sup.+ and P.sup.+ impurities are diffused into the substrate. An insulating layer is then grown over the oxide, P.sup.+, and N.sup.+ regions. The insulating layer is etched back, uncovering the substrate, P.sup.+ region, and a portion of the N.sup.+ region. Similarly, a thick aluminum layer is deposited and etched back to form a first connection layer. Subsequently, an insulating layer is formed over the first insulating layer.

Abstract: An electrostatic discharge protection circuit is used to protect an internal circuit that is electrically connected to an integrated circuit pad. The electrostatic discharge protection circuit comprises an erasable programmable read only memory, a capacitor, and a load element. The erasable programmable read only memory is provided with one source/drain connected to the pad, another source/drain connected to a power node, and a control gate. The capacitor is connected between the control gate and the pad while the load element is connected between the control gate and the power node. When electrostatic discharge stress occurs to the pad, the erasable programmable read only memory enters breakdown and is programmed by means of coupling effect through the capacitor. Under normal operation, the erasable read only memory is turned off via the load element.

Abstract: A silicon-rectifier integral with either an NMOS transistor or a PMOS transistor (together which constitute an output buffer) is disclosed. If integral with the NMOS transistor, the silicon-controlled rectifier is provided with the emitter and base of the NPN bipolar junction transistor acting as the source and bulk of the NMOS transistor. On the other hand, if integral with the PMOS transistor, the silicon-controlled rectifier is provided with the emitter and base of the PNP bipolar junction transistor acting as the source and bulk of the PMOS transistor.

Abstract: An electrostatic discharge protection circuit comprises a semiconductor layer of a first conductivity type, a floating semiconductor layer of a second conductivity type, a first doped region of the first conductivity type, a first doped region of the second conductivity type, a second doped region of the second conductivity type, a gate structure, and a second doped region of the first conductivity type. The floating semiconductor layer of a second conductivity type is in contact with the semiconductor layer of a first conductivity type to establish a junction therebetween. The first doped region of the first conductivity type is formed in the semiconductor layer of a second conductivity type and connected to a first node. The first doped region of the second conductivity type is formed in the semiconductor layer of a first conductivity type and connected to a second node. The second doped region of the second conductivity type spans the junction.

Abstract: An electrostatic discharge protection circuit comprises an NMOS transistor and a silicon-controlled rectifier. The NMOS transistor is configured with one source/drain region connected to a first node, and its gate as well as another source/drain region connected to a second node. The silicon-controlled rectifier comprises a PNP transistor, an NPN transistor, and a resistor. The PNP transistor is provided with a first emitter connected to the first node, a first base disconnected from the first node, and a first collector. The NPN transistor is provided with a second emitter connected to the second node, a second base connected to the first collector and a second collector connected to the first base. However, the resistor is connected between the second base and the second node. The NMOS transistor enters breakdown to trigger the silicon-controlled rectifier to conduct a discharge current when electrostatic discharge stress occurs between the first node and the second node.

Abstract: To protect an input buffer from gate-oxide breakdown failure during an ESD/EOS event, an inventive secondary protection circuit is disclosed. In one embodiment, the protection circuit includes a first switch terminal connected to a pad, a second switch terminal connected to the buffer of an internal circuit, a control terminal, and an RC circuit connected between the control terminal and the supply voltage Vcc. The RC circuit delays a propagation of an ESD/EOS voltage from Vcc to the control terminal, so as to delay a generation of a conductive path between the first and second switch terminals until the ESD/EOS event lapses.

Abstract: A lateral silicon-controlled rectifier, which comprises a semiconductor layer of a first conductivity type, a floating semiconductor layer of a second conductivity type, a first doped region of the first conductivity type, a first doped region of the second conductivity type, and a second doped region of the first conductivity type, is disclosed. The floating semiconductor layer of a second conductivity type is in electrical contact with the semiconductor layer of a first conductivity type to establish a junction. The first doped region of the first conductivity type is formed in the semiconductor layer of a second conductivity type and coupled to a first node. Both the first doped region of the second conductivity type and the second doped region of the first conductivity type are formed in the semiconductor layer of a first conductivity type and coupled to a second node.

Abstract: An ESD protected structure and method of its fabrication are disclosed. A heavily doped polycrystalline silicon region of a first conductivity type is disposed on a substrate surface and is connected to a power supply voltage. A lightly doped region, of the first conductivity type, is disposed below the substrate surface and below the polycrystalline silicon region. A first heavily doped region, of the first conductivity type, of a first MOS device is disposed below the substrate surface, and contained entirely within the lightly doped region. A second heavily doped region, of the first conductivity type, of a second MOS device, is disposed below the substrate surface, and separated from the first region by a portion of the lightly doped region and a second conductivity type doped portion of the substrate.

Abstract: An electrostatic discharge protection circuit protects an internal circuit that is coupled to a pad from electrostatic discharge damage. The electrostatic discharge protection circuit comprises a PNP transistor, a NPN transistor, and a P-type flash memory cell. The PNP and NPN transistors have an emitter, a base, and a collector, respectively. The PNP transistor is configured with its emitter connected to a power node, its base connected to the collector of the NPN transistor, its collector connected to the base of the NPN transistor. The emitter of the NPN transistor is connected to a circuit node. The flash memory cell is configured with a drain connected to the base of the NPN transistor, a source connected to the power node, and a control gate coupled to the power node. When electrostatic discharge stress occurs at the pad, the P-type flash memory cell enters breakdown to be programmed and triggers the conduction of the transistors.

Abstract: An apparatus and method for use in a semiconductor memory device to reduce internal circuit damage resulting from the effects of electro-static discharge (ESD) on a bitline pull-up or other type of circuit. Each of a plurality of bitlines in the memory device are coupled to a source terminal of a corresponding N-type MOSFET. Each source terminal is formed in a separate corner portion of at least one active region of the memory device, and is coupled to a given bitline via a bitline contact arranged in the corner portion. Each drain terminal of the N-type MOSFETS is formed from another portion of the active region and is coupled to a VDD supply of the memory device via a VDD contact. A gate terminal of a given MOSFET is formed from a polysilicon gate region overlying a channel in the active region. The gate region has an approximately 90.degree.