Abstract: A cascaded diode acting as all ESD protection device with reduced substrate leakage current is disclosed. The cascaded diode is composed of a chain of coupled similar elemental diodes, each composed of an n-well in a p-substrate, the n-well having p regions and n regions, and a deep n-well disposed under and connected to the n-well. The first elemental diode has its p region electrically connected to a pin or pad that is the higher potential end of a portion of an integrated circuit to be protected, its n region electrically connected to the p region of an intermediate elemental diode. The p region of an intermediate diode is connected electrically to the n region of the preceding elemental diode and the n region of an intermediate elemental diode is connected electrically to the p region of the following elemental diode.

Abstract: Within both an anti-fuse structure and a method for operating the anti-fuse structure there is employed a semiconductor substrate having a first region adjoining a second region, where there is formed a metal oxide semiconductor field effect transistor within and upon the first region of the semiconductor substrate and a metal oxide semiconductor capacitor within the upon the second region of the semiconductor substrate. Further, within the anti-fuse structure: (1) a gate dielectric layer within the metal oxide semiconductor field effect transistor is thicker than a capacitive dielectric layer within the metal oxide semiconductor capacitor; and (2) the metal oxide semiconductor capacitor is formed employing as a first capacitor plate a doped well within the semiconductor substrate of equivalent polarity with and overlapping with a source/drain region within the metal oxide semiconductor field effect transistor.

Abstract: The present invention provides an electrostatic discharge (ESD) protection circuit. The ESD protection circuit comprises a semiconductor-controlled-rectifier (SCR) and a non-volatile memory. The SCR comprises an anode, an anode gate and a cathode. The anode and the cathode are coupled to a first node and a second node, respectively. The non-volatile memory comprises a floating gate and two source/drains. The two source/drains are respectively coupled to the cathode and the anode gate. The floating gate is provided with a predetermined charge to decrease the trigger voltage of the SCR.

Abstract: A method for forming an electrical metal fuse for use with a semiconductor integrated circuit device. At least two varying trench metal depths may be formed on a substrate to configure the electrical metal fuse thereon. Additionally, at least two different widths of single metal lines, may be configured on the substrate. As a result of the two different trench depths and two different widths of metal formed thereon to create the electrical metal fuse, increases in current density gradients and thermal gradients thereof can be generated. The trench metal depths and width of metal are formed from copper. The electrical metal fuse generally comprises a current density ratio greater than 10 to 1.

Abstract: A seal ring structure having an electrostatic discharge protection function, suitable for a conductive first-type substrate which has a bias provided by a second power source. The new seal ring scheme including a conductive second-type doped diffusion region located on the first-type substrate; and a metal conductive structure, comprising at least a metal layer and a connection conductor, wherein the connection conductor is connected to the conductive second-type doped diffusion region and to a bias provided by a first power source and to the metal layer.

Abstract: A high-voltage tolerance input buffer and a high-voltage ESD protection circuit connected to a pad of an integrated circuit for preventing rapid gate oxide aging. The high-voltage tolerance input buffer of the present invention comprises a voltage-sharing circuit and a switch circuit, wherein the voltage-sharing circuit is connected between the pad and a power rail and generates a reference voltage not higher than the voltage of the pad. The switch circuit is connected to the voltage-sharing circuit and comprises a control gate to control the switching operation of the switch circuit according to the reference voltage. The present invention can be implemented to solve the rapid gate oxide aging problem without incurring any change in the original process flow by employing a voltage-sharing circuit.

Abstract: A cascaded diode acting as an ESD protection device with reduced substrate leakage current is disclosed. The cascaded diode is composed of a chain of coupled similar elemental diodes, each composed of an n-well in a p-substrate, the n-well having p regions and n regions, and a deep n-well disposed under and connected to the n-well. The first elemental diode has its p region electrically connected to a pin or pad that is the higher potential end of a portion of an integrated circuit to be protected, its n region electrically connected to the p region of an intermediate elemental diode. The p region of an intermediate diode is connected electrically to the n region of the preceding elemental diode and the n region of an intermediate elemental diode is connected electrically to the p region of the following elemental diode.

Abstract: The present invention provides a method for fabricating an ESD device. First, a substrate undergoes first implantation to form a first first-type well comprising an electrostatic discharge region. Next, second implantation is performed on the substrate and the electrostatic discharge region to form a second first-type well and an ESD device. Finally, gates, sources, and drains are formed to complete the process.

Abstract: The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in an npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with an unique emitter design layout. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements.

Abstract: A fusible link device and a method of making same. The fusible link device comprising a poly layer having a center undoped portion and two doped end portions. The center undoped portion having a first resistance and the two doped end portions each having a second resistance that is lower than the first resistance. A silicide layer is formed over the poly layer with the silicide layer having a third resistance lower than the second resistance. The silicide layer agglomerating to form an electrical discontinuity within a discontinuity area in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased. The agglomeration of the silicide layer occurring over the center undoped portion of the poly layer. Contacts are electrically coupled to the two doped poly layer end portions for receiving the programming potential.

Abstract: An electrostatic discharge protection circuit, comprising a semiconductor-controlled rectifier and a PMOS device. The semiconductor-controlled rectifier, coupled between two nodes, has an N-type semiconductor layer. The PMOS device, integrated with the semiconductor-controlled rectifier to share a first P-type doped region, has a PNP device located in the N-type semiconductor layer. When one of the nodes is coupled to the electrostatic discharge power, the PNP device will conduct to trigger the semiconductor-controlled rectifier.

Abstract: A method of fabricating an HV-I/O ESD MOS device comprising the following steps. A structure having a first device region, a second device region and an HV-I/O ESD MOS device region is provided. A gate is formed over an oxide layer within the first device region. A gate is formed over an oxide layer within the second device region. A gate is formed over an oxide layer within the HV-I/O ESD MOS device region. The first device gate oxide layer is thinner than the second device gate oxide layer and the HV-I/O ESD MOS device gate oxide layer. The gate and oxide layers within each region have exposed side walls. An LV-LDD mask is formed over the gate and the structure within the second device region. An LV-LDD implant is performed into the structure adjacent the first device gate and the HV-I/O ESD MOS device gate to form first device LV-LDD implants and HV-I/O ESD MOS device LV-LDD implants. The LV-LDD mask is removed. An HV-LDD mask is formed over the gate and the structure within the first device region.

Abstract: An ESD protection circuit based on a modification of conventional silicon controlled rectifier (SCR) for preventing integrated circuits from ESD damage. A first N-well, which has a second N-type doped region and third P-type doped region, is formed in a P-type substrate. A fourth N-type doped region and fifth doped region are formed adjacent to the first N-well in the substrate. A first conducting structure is formed on the second N-type doped region and connected to an anode. A second conducting structure is formed on the fourth N-type doped region and fifth P-tape doped region and connected to a reference potential.

Abstract: A latch-up protection circuit for an integrated circuit powered through a first power rail and a second power rail is disclosed, the integrated circuit having at least one semiconductor bulk of a conductivity type. The latch-up protection circuit comprises a control circuit and a switch circuit. The control circuit is connected to the first power rail and the second power rail for detecting a relative voltage therebetween and generating a first control signal and a second control signal. The switch circuit connected to the first power rail and the control circuit. When the relative voltage is greater than a first predetermined value, the switch circuit in response to the first control signal electrically connects the first power rail with the at least one semiconductor bulk. When the relative voltage is smaller than the first predetermined value, the switch in response to the first control signal electrically disconnects the first power rail from the at least one semiconductor bulk.

Abstract: The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in an npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with an unique emitter design layout. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements.

Abstract: A novel electrostatic discharge (ESD) protection device used for mixed voltage application is disclosed. A primary ESD device and a MOS transistor stack are respectively coupled to the input/output pad. The MOS transistor stack is formed in a cascode configuration comprising a first MOS transistor and a second MOS transistor form in different active areas. The drain region of the first MOS transistor is coupled to the input/output pad and the gate region is coupled to a low power supply. The second drain region of the second MOS transistor is coupled to the source region of the first MOS transistor, while the gate region and the source region grounded. The primary ESD device is selected with a junction breakdown voltage no more than the lowest junction breakdown voltage of the MOS transistor stack, so that the primary ESD device enters snapback prior to the MOS transistor stack.

Abstract: According to the object, the present invention provides an electrostatic discharge (ESD) circuit, coupled between a pad and a power line. The ESD protection circuit comprises a bipolar junction transistor (BJT) . The BJT comprises a collector region having a first conductivity type, formed in a substrate, in contact with a buried layer having the first conductivity type, and coupled to the pad to become the collector of the BJT, a base region having the second conductivity type, formed on the buried layer to become the base of the BJT, and an emitter having the first conductivity type, formed in the base region and coupled to the power line to become the emitter of the BJT. The emitter has a plurality of parallel first regions and a second region connecting the first regions.

Abstract: A method of forming an electrical metal fuse comprising the following steps. A substrate is provided. A first patterned dielectric layer is formed over the substrate. The first patterned dielectric layer having at least one first opening exposing at least a portion of the substrate. A first planarized structure is formed within the at least one first opening. A second patterned dielectric layer is formed over the first planarized structure. The second patterned dielectric layer having a second opening exposing at least a portion of the first planarized structure. A second planarized structure is formed within the second opening whereby the first planarized structure and the second planarized structure comprise the electrical metal fuse. The electrical metal fuse having a middle portion, having a thickness and a width, between two end portions each having a thickness and a width. The thickness and width of the middle portion being less than the respective thickness and width of the end portions.

Abstract: A fusible link device and a method of making same. The fusible link device comprising a poly layer having a center undoped portion and two doped end portions. The center undoped portion having a first resistance and the two doped end portions each having a second resistance that is lower than the first resistance. A silicide layer is formed over the poly layer with the silicide layer having a third resistance lower than the second resistance. The silicide layer agglomerating to form an electrical discontinuity within a discontinuity area in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased. The agglomeration of the silicide layer occurring over the center undoped portion of the poly layer. Contacts are electrically coupled to the two doped poly layer end portions for receiving the programming potential.

Abstract: An integrated circuit package includes a semiconductor chip, bonding pads on the semiconductor chip, a metal lead frame containing electrically with the semiconductor chip, a plurality of wired pins wire-bonded respectively to the bonding pads, and at least one non-wired pin. The non-wired pin is wire-bonded to the metal lead frame to prevent electrostatic discharge failure of the integrated circuit package due to electrostatic discharge stressing of the non-wired pin.