Abstract: A semiconductor memory device comprises read-out circuits responsive to first column address decoded signals for transferring data bits from selected bit lines to data line pairs, selector circuits responsive to second column address decoded signals for transferring a data bit from selected one of the data line pairs to a read data amplifier circuit and a precharge circuit coupled between a source of power voltage level and the data line pairs for charging the selected data line pair before transmission of the data bit to the selected data line pair, and the precharge circuit isolates the data line pair from the source of power voltage level so that potential difference indicative of the data bit rapidly takes place on the selected data line pair.

Abstract: A semiconductor integrated circuit device has a first internal voltage controlling circuit which lowers an external power source voltage and produces a predetermined internal power source voltage. The device further has a second internal voltage controlling circuit formed by an internal-voltage drop detection circuit for detecting the lowering of the internal power source voltage from a predetermined reference voltage and a switching circuit for causing the external power source voltage to be directly connected to an internal voltage output terminal based on an output from the internal-voltage drop detection circuit. The internal power source voltage is maintained close to the required value thereby preventing a deterioration of circuit performance even when the external power source voltage drops close to the internal power source voltage.

Abstract: A DRAM according to the invention is provided with a memory cell array formed by arranging in the row and column directions one-transistor-one-capacitor type memory cells; bit lines, precharged at a prescribed timing, for performing the transfers of write-in/read-out data to and from the memory cells; a sense amplifier including a first transistor, whose drains are connected to the bit lines to bias the substrate to a prescribed potential, and a second transistor whose drains and sources are connected to the sources of the first transistor and a ground potential point, respectively, whose gates receive an activation control signal and whose substrate is biased to the same potential as the first transistor is, for amplifying the signals of said bit lines when activated; an intermediate potential generating circuit for supplying an intermediate potential which is substantially equal to 1/2 of the source potential to the opposite electrodes of said memories and to the bit lines; a power turn-on sensing circuit f

Abstract: A dynamic random access memory device negatively biases the semiconductor substrate, and a substrate bias system incorporated therein produces a negative bias voltage from an external power voltage level for accelerating the negative biassing operation before an internal power voltage is sufficiently developed by an internal step-down circuit incorporated therein; however, after the development, the substrate bias system produces the negative bias voltage from the internal power voltage so as to be less affectable by fluctuation of the external power voltage level.

Abstract: A power supply circuit for a DRAM has a power-on detection circuit which detects when an external power supply potential reaches a predetermined potential and produces first and second detection signals, and an internal power supply circuit which generates an internal power supply potential.

Abstract: A semiconductor integrated circuit device is equipped with an internal power source unit for distributing an internal power voltage level between component circuitries, and the internal power voltage level is regulated to a variable reference voltage level, wherein a first main voltage regulator regulates the variable reference voltage level to a primary reference voltage level before reaching a threshold voltage level; however, after the primary reference voltage level becomes lower than the threshold voltage level, a latching circuit supplies an activation signal to a second main voltage regulator, and the second main voltage regulator regulates the variable reference voltage level to a secondary reference voltage level so that the second main voltage regulator continuously controls the variable voltage level without any abrupt transition, thereby allowing the internal power source unit to adjust the internal power voltage level to an arbitrary point.

Abstract: The semiconductor memory device according to the present invention has a memory cell array which includes a plurality of memory cells provided in array form and a plurality of bit lines and word lines that are respectively connected to the memory cells, where the bit lines are arranged so as to form a group of paired lines, sense amplifiers which are provided one for each of the bit line pairs, for amplifying the potential difference between the lines of the bit line pair in response to an activating signal, a delay circuit which uses said activating signal as its input signal, for generating a selection signal by giving to said activating signal a delay time that varies in response to a control signal from a switching circuit, and selection switch means for connecting a predetermined one of said bit line pairs and I/O lines in response to said selection signal.

Abstract: An output gate according to the present invention includes a CMOS gate composed of a P-MOS transistor connected at a source to an external power supply and a first N-MOS transistor connected at a source to ground, and a second N-MOS transistor connected between ground and the first N-MOS transistor by a source-drain path. The second N-MOS transistor is connected at a gate to an external power supply.

Abstract: A power-on detecting circuit produces a power-on signal upon power-on event for initializing internal component circuits, and comprises a timing generating unit for producing a timing signal when a power voltage level reaches a predetermined voltage level, a monitoring unit for producing an enable signal when a step-down power voltage level reaches a constant level, and a signal generating unit for producing the power-on signal in the concurrent presence of the enable signal and the timing signal, thereby guaranteeing the initialization of the internal component circuits.

Abstract: A 16 megabit dynamic random access memory device is active with an internal power voltage lower than an external power voltage for preventing extremely thin gate oxide films of the component field effect transistors from damage, a field effect transistor is coupled between an input terminal applied with an external signal as high as the external power voltage and an input logic gate for producing an internal signal as low as the internal power voltage, and the field effect transistor is supplied at the gate electrode with the internal power voltage so that the external signal steps down before reaching the input logic gate.

Abstract: A dynamic random access memory device can enter a diagnostic mode of operation to see whether or not undesirable short-circuit takes place in a word line and/or a control signal line for transfer gates between bit lines and a sense amplifier unit, and a built-in testing operation discriminating unit discriminates the testing operation on the word lines and the control signal lines from other testing operations for causing a power supply system to interrupt electric power to a row address decoder unit and a driver unit for the control signal lines so that voltage level on a word line and/or a control signal line is rapidly decayed due to the short-circuit, thereby screening out the defective products before the delivery from the manufacturer.

Abstract: A semiconductor integrated circuit which comprises a detection circuit for detecting a voltage of a semiconductor substrate and a negative voltage generating circuit for generating a negative voltage to be supplied to the substrate in accordance with an output signal of the detection circuit. The detection circuit includes a first P-channel MOS transistor having a gate connected to a ground potential, a source connected to a power source and a drain connected to a node coupled to the detection circuit, and a second P-channel MOS transistor having a gate connected to the substrate, a source connected to the node and a drain connected to ground. Current does not flow from the external power source to the substrate, so that, even if the negative voltage generating circuit does not have its electric current supplying capacity increased, the voltage of the substrate can be detected.

Abstract: A bootstrap circuit with a word line of a semiconductor memory device comprises a bootstrap unit having a bootstrap capacitor coupled at one electrode thereof to an output node and supplied from an input node with an input signal, and responsive to a booting signal of a power voltage level supplied to the other electrode of the bootstrap capacitor for bootstrapping an output voltage at the output node over the power voltage to a first predetermined level in cooperation with a load capacitor; a constant voltage source operative to produce a second predetermined voltage level higher than the low voltage level and lower than the booting signal; and a switching unit operative to supply the booting signal to the other electrode in the presence of the input signal and to feed the second predetermined voltage level to the other electrode in the absence of the input signal, wherein the other electrode of the bootstrap capacitor varies the voltage level between the power voltage level and the second predetermined volt

Abstract: A semiconductor memory device having a redundant cell array and provided with an improved indicating circuit of the selection state of the redundant cell array is disclosed. The memory device comprises a tri-state type output circuit for generating read-out data from the selected memory cell at an output terminal, a detection circuit for generating a detection signal when the memory cell of the redundant cell array is selected and a control circuit for disenabling the output circuit thereby to make the output terminal at a high impedance state in response to the detection signal.