Abstract: In a magnetic random access memory, a cross point cell array of memory cells is arranged in a matrix of columns and rows, and each of the memory cells has a magneto-resistance element. A column of dummy memory cells is provided, and each of the dummy memory cells has a magneto-resistance element. Word lines are provided for the rows of the memory cells and the dummy memory cells, respectively, and bit lines are provided for the columns of the memory cells, respectively. A dummy bit line is provided for the column of dummy memory cells. A read circuit is connected with the cross point cell array and the dummy bit line.

Abstract: A semiconductor device includes an MPU (Micro Processing Unit) section, a DRAM (Dynamic Random Access Memory) section, a plurality of address registers, and a plurality of address delay compensating units. The MPU section is provided on a chip to output a clock signal and an address signal. The DRAM section is provided on the chip to input the clock signal and the address signal. Each of the plurality of address registers latches the address signal in response to the clock signal. Each of the plurality of address delay compensating units is provided in a previous stage to the plurality of address registers and compensates for an address signal transmission delay time such that the address signal transmission delay time falls within a predetermined range. The address signal transmission delay time indicates a time elapsed before the each address register inputs the address signal after the MPU section outputs the address signal.

Abstract: A pair of memory elements form a unit cell and these elements are magnetized in opposite directions. At the time of read a voltage of V1 is applied to a word line WL0 and a voltage of V2 is applied to the word line/WL0. Further a specific bit line is connected to a read circuit 22 and the bit line is virtually grounded to Vg=(V1+V2)/2. Therefore, current Is passed through the bit line is as follows: Is=Vs·(Rb−Ra)/(Ra·Rb), wherein the resistance value of the memory element 1a is Ra, the resistance value of the memory element 1b is Rb. Thus, if a direction of the current is detected by the read circuit, information written in the unit cell can be read. Thus, a non-volatile magnetic memory whose cell configuration is simple, and which can be integrated with high density and has a read circuit having a small surface area and low power consumption, can be obtained.

Abstract: Disclosed is a semiconductor memory device which uses tunneling magnetoresistive element as memory cells and eliminates the temperature dependencies in a write margin and read margin in such a way as to be able to accurately output a write current at the time of writing the memory cells. The semiconductor memory device is constructed in such a way that main bit lines or main word lines are laid out so as to cross bit lines or word lines perpendicularly, and a main bit line selector or a main word line selector which respectively selects the main bit line or the main word line is arranged outside a memory cell array.

Abstract: For use in designing a logic circuit of a semiconductor device, a library (10) memorizes not only a delay value (TYP, MIN, or MAX) for each of signal paths of a circuit element of the logic circuit but also a standard deviation (&sgr;CHIP or &sgr;TR) of a variation of the delay value for each of the signal paths of the circuit element. Instead of the standard deviation, the library may memorize a variance of the variation. The variance is given by (&sgr;CHIP)2 or ( &sgr;TR)2 when the variation is a normal distribution.

Abstract: A semiconductor integrated circuit device has a plurality of basic cells. The basic cells are placed in a matrix form, and are formed on a semiconductor substrate. Each of the basic cells includes a wire selection portion and a logic gate portion. The logic gate portion has a MOS transistor. The wire selection portion has a thin-film transistor serving as a transfer gate. The wire selection portion is placed over the logic gate portion via an interlayer insulating film.

Abstract: A semiconductor memory apparatus using tunnel magnetic resistance elements comprises a plurality of cell arrays. When data is read from a cell in one of the cell array, a word line connected to the cell is connected to a voltage source, a bit line connected to the cell is connected to an input of a sense amplifier, word lines in the cell array concerned except for the word line connected to the cell and bit lines in the cell array concerned except for the bit line connected to the cell are isolated. A subtracter subtracts an offset current which is generated in another cell array from a current flowing from the bit line connected the cell. An integrator integrates the result of the subtraction. A comparator, a read current value register, and a reference value register performs self-reference reading method on the result of the integration.

Abstract: Semiconductor integrated circuit includes a MPU and a cache memory implemented by a plurality of DRAM macro blocks each disposed between the MPU and bonding pads of the chip. Each DRAM macro block has a redundancy function for replacing a defective row with a redundancy row of memory cells. A plurality of fuse blocks each for storing the row address of the defective row are arranged in a row, with the elongate sides of each of the fuse blocks extending parallel to the signal lines extending between the MPU and the bonding pads. The arrangement allows a large number of signal lines to pass the space between the fuse blocks, thereby allowing a smaller chip size.

Abstract: A power-on circuit and a resetting method by which resetting of a circuit through which flows direct current upon resetting can be achieved stable state without causing a large current to flow in the circuit. For resetting a circuit through which flows the direct current at the time of resetting, such as a circuit for resetting a fuse on power source on, there is provided a power-on circuit generating a one-shot signal on power source on, in which two or more one-shot signals are provided and resetting is carried out by at least two partial operations to achieve stable resetting without flowing a larger current.

Abstract: A large scale semiconductor integrated circuit, implemented on a chip, includes an MPU and a DRAM cache memory including a plurality of DRAM macro blocks located around the MPU. The DRAM macro block has a redundancy function for which a plurality of fuses are disposed for cut-out by laser beams. The lower metallic layers implement source lines for power and ground to the DRAM macro blocks, whereas a topmost metallic layer implements source lines for the MPU. The topmost metallic layer circumvents areas of the chip where portions of a metallic layer constituting fuses for implementing the redundancy function are located.

Abstract: The present invention relates to a semiconductor storage device in which data retention current consumption can be reduced. This device comprises memory cells, an internal power supply circuit for supplying an internal voltage HVC to the memory cells, transistors for halting the internal power supply circuit, and a switch circuit (transistors) for selectively supplying one of the internal voltage HVC or an externally supplied voltage HVC_EXT to the memory cells. When the memory cells are in a stand-by state (SLEEP=1) and are not engaged in a refresh operation, the internal power supply circuit is halted, and the externally supplied voltage HVC_EXT is supplied to the memory cells.

Abstract: For use in designing a logic circuit of a semiconductor device, a library (10) memorizes not only a delay value (TYP, MIN, or MAX) for each of signal paths of a circuit element of the logic circuit but also a standard deviation (&sgr;CHIP or &sgr;TR) of a variation of the delay value for each of the signal paths of the circuit element. Instead of the standard deviation, the library may memorize a variance of the variation. The variance is given by (&sgr;CHIP)2or (&sgr;TR)2 when the variation is a normal distribution.

Abstract: A semiconductor integrated circuit device has a plurality of basic cells. The basic cells are placed in a matrix form, and are formed on a semiconductor substrate. Each of the basic cells includes a wire selection portion and a logic gate portion. The logic gate portion has a MOS transistor. The wire selection portion has a thin-film transistor serving as a transfer gate. The wire selection portion is placed over the logic gate portion via an interlayer insulating film.

Abstract: The present invention provides a multi-value DRAM that does not require additional surface area, has a low cost, and has a good yield. A 4-value memory cell is disposed at the intersection of a word line WL and sub-bit lines BLNx0. A potential corresponding to 11, 10, 01, and 00 is written to the dunmmy cell disposed at the intersection of the sub-bitline connected to the dummy word lines DWLN and DWLT and the SSAs 31 and 32. The SSA30 outputs the data in the memory cell and the reference levels 0x and 1x on the sub-bit lines BLTx0 to the main bit lines GBLN0 and GBLT0. The SSA31 balances the potentials of the dummy cell connected to both dummy word lines and outputs the reference levels 11 and 10 to the main bit line GBLN4. Similarly, the SSA32 balances the potentials of both dummy cells, and outputs the reference levels 01 and 00 to the main bit line GBLT4. The MSA 33 discriminates the upper bit UPBIT and the lower bit LWBIT of the data based on the potentials on the 4 main bit lines.

Abstract: A semiconductor memory device has: a memory cell array for relief 201 which stores tag (TAG) information written from a nonvolatile memory 200 for identifying defective bit cells in the basic memory 110, 110b and provides a plurality of memory cells (data) for replacing the defective bit cells in bits; an address converter 203 for allocating external addresses to an index portion and a tag portion; a decoder 202 for decoding the index portion and outputting a word line signal to the memory cell array 201; a comparator 204 for comparing the allocated tag portion with the tag information inside the memory cell array 201 specified by an output word line signal of the decoder 202; and a selector 205 for selecting and connecting either of memory cells in the basic memory 110, 110b and memory cells in the memory cell array 201 with the outside on the basis of a hit flag outputted from the comparator 204.

Abstract: A semiconductor memory device exchanges a defective address for a non-defective address so as to ensure continuous access to non-defective address areas. The memory cell array comprises a plurality of memory cell areas. An address decoder selects one of the memory cell areas. An address exchanging circuit exchanges a defective area address for a non-defective area address, and supplies the exchanged area address to the address decoder. Continuous access to non-defective areas is thereby obtained.

Abstract: An integrated-circuit device comprises a combination of a microprocessor in the form of a circuit cell having a prescribed shape as an existing microprocessor and cache memories and a tag memory each in the form of a circuit cell. The tag memory have the same row addresses as the cache memories, and some of the row addresses are converted to column addresses. The tag memory is of a structure in which a basic structure similar to a conventional structure is divided into a plurality of parts in one of x and y directions, and the parts are arrayed in the other of the x and y directions. The tag memory thus shaped can be placed in a dead space on a circuit board, and hence an undesirable dead space can be eliminated from the integrated-circuit device.

Abstract: A plurality of bit line pairs are provided in a semiconductor memory device. A plurality of memory cells are connected to the first bit line pairs. Also, in the semiconductor memory device, there are provided a first sense amplifier, a second bit line pair and a second sense amplifier. The first sense amplifier reads and amplifies a potential difference between the first bit line pair. A signal output from the first sense amplifier is transmitted to the second bit line pair. The second sense amplifier amplifies a potential difference between the second bit line pair. A precharge circuit is built in the second sense amplifier. The first bit line pairs are precharged by the precharge circuit.

Abstract: A semiconductor memory device (100) includes a normal cell array and a redundant cell array. When a normal cell array location is to be replaced by selecting the redundant cell array, a first circuit (120) outputs a one-shot signal (PBLST) to a redundant block selection circuit (118). The redundant block selection circuit (118) activates a redundant precharge stop signal (RDPBL) without waiting for a redundant cell decoder (110) decoding result. The redundant cell decoder (110) result indicates whether the redundant cell array is selected or not selected. Accelerated accesses to the redundant cell array can result, improving overall access speed for the semiconductor memory device (100).

Abstract: A DRAM having open-bit-lines wherein noise to be impressed to word-lines can be restricted within a certain range. The DRAM includes a logic reversing circuit for reversing the logic levels of a portion of bits in a bit sequence to be stored, and a circuit for recording and detecting whether the logic levels of the portion of the bits is reversed for each stored bit sequences. Logic reversal takes place when one logic level predominates the bits of the bit sequence. Examples of the portion of bits in a bit sequence subject to logic level reversal would be the odd-numbered bits or even-numbered bits in a sequence.