Abstract: A semiconductor memory device is grouped into a plurality of flexible macro chips. Under the circumstances, a clock input first stage circuit is arranged in a first flexible macro chip to supply an internal reference clock signal and a first internal clock signal in response to an external reference clock signal. Further, a group of command input first stage circuits are collectively arranged in a second flexible macro chip different from the first flexible macro chip. In this event, the the first internal clock signal is directly supplied to the command input first stage circuits so as to input a command signal.

Abstract: A semiconductor memory device (100) having reduced logic gates for selecting sense amplifier columns (102-0 to 102-2) is disclosed. Sense amplifier columns (102-0 to 102-2) are selected according to block address values X5 to X0. The order in which sense amplifier columns (102-0 to 102-2) are selected corresponds to a gray code in the lower two significant block address values (X1 and X0). In this arrangement, X1 can be applied to a NAND gate 110-0 within sense amplifier selecting circuit 106-1 as predecoded signal C1. X0 can be applied to a NAND gate 110-1 within sense amplifier selecting circuit 106-2 as predecoded signal C2. The use of predecoded values (X0 and X1) instead of decoded values can reduce the logic required to select the sense amplifier columns (102-0 to 102-2).

Abstract: A semiconductor memory device includes a plurality of bus lines, normal memory cell arrays, data amplifiers for amplifying data read from the normal memory cell arrays, redundancy memory cell arrays, and redundancy data amplifiers for amplifying data read from the redundancy memory cell arrays. First bus selectors selectively connect the normal data amplifiers to the bus lines and second bus selectors selectively connect the redundancy data amplifiers to the bus lines.

Abstract: A semiconductor dynamic random access memory device has first open bit lines arranged in parallel and second open bit lines respectively paired with the first open bit lines so as to form bit line pairs and a sense amplifier shared between the bit line pairs so as to increase the magnitude of a potential difference indicative of a data bit sequentially supplied from the bit line pairs, and either high or low level indicative of the data bit is supplied to both first and second bit lines of the selected bit line pair upon completion of the sense amplification, thereby equalizing electric influence on the adjacent open bit lines.

Abstract: A semiconductor memory device is disclosed, in which a memory region which can not be used due to existence of defective bit line is reduced. In a DRAM of a double word line system, when there is a defective bit line 103 in a certain block thereof, only a memory region 104 in a right or left portion of the block to which the defective bit line 103 belongs is made invalid and a region on the other side is made valid. In this case, clusters are constructed with the valid memory region by converting the uppermost bits of a row address and the uppermost bits of a column address by means of an address conversion circuit.

Abstract: A semiconductor memory device has a main word decoder for selecting a cluster from a memory cell block, and the main word decoder stores pieces of control data information each representative of whether the cluster is defective or non-defective; while an external device is sequentially accessing the clusters, the main word decoder skips the defective clusters on the basis of the piece of control data information, and accelerates the data access to the clusters.

Abstract: A semiconductor memory device including a plurality of sub-bit lines, a sense amplifier provided in common to the plurality of sub-bit lines which receives a data signal from a first one of the plurality of sub-bit lines, a main-bit line operatively coupled to the sense amplifier to receive an output of the sense amplifier, and a data latch circuit provided to latch data appearing on the main-bit line. The device further comprises a circuit for transferring a data signal of a second one of the plurality of sub-bit lines to the sense amplifier when the data latch circuit is being accessed to read out data latched in the data latch circuit.

Abstract: A data refresh is indispensable for a semiconductor dynamic random access memory device, and electric charges are recycled from bit line pairs for a row of memory cell arrays to power supply lines for bit line drivers associated with the next row of memory cell arrays and from bit line pairs for the next row of memory cell arrays to power supply lines for the row of memory cell arrays, thereby reducing power consumption in the data refresh.

Abstract: In a semiconductor memory device including: a plurality of sub word lines, a plurality of sub word decoders each connected to one of the sub word lines, a plurality of pairs of main word lines each pair connected to a number of the sub word decoders, and a plurality of main word decoders each connected to one of the pairs of main word lines, each of the main word decoders sets voltages at a respective pair of the pairs of main word lines different from each other in a selection mode and sets the voltages at a respective pair of the pairs of main word lines the same as each other in a non-selection mode.

Abstract: In a semiconductor device, a chip is constructed by a plurality of sub chips adjacent to each other on a wafer, each of the sub chips being able to carry out the same operation individually, and one neighbor detecting circuit is provided in each side of sub chips for detecting the presence or absence of an adjacent sub chip.

Abstract: A dual port memory has a plurality of memory cell arrays. Plural bit lines for one word are divided into k groups each including m bit lines, and k data busses are commonly provided for all of the memory cell arrays. Bit selecting circuits control data transfer between the data busses and the memory cell arrays. A shift register circuit includes a plurality of partial shift registers which are serially connected with each other and each of which includes serially connected registers corresponding to the data busses. The shift register circuit carries out parallel data transfer between the data busses and each of the partial shift registers, and serial data transfer between one of the partial shift registers and an outside circuit. A dual port memory is provided in which the number of circuit elements and the surface size of memory chips can be reduced while maintaining a high speed of operation.

Abstract: A semiconductor random access memory device is subjected to a parallel testing operation to see whether or not a defective memory cell is incorporated in the semiconductor random access memory device; in the parallel testing operation, a test bit of logic "1" level is sequentially written into a first predetermined address of each of data storage blocks by changing a column address, then, a test bit of logic "0" level is written into a second predetermined address of each of the data storage blocks by changing the column address again, and the write-in operation is repeated so as to form a checker-like bit pattern in each data storage block; after the formation of the test pattern, the test bits are sequentially read out from the first predetermined address of the data storage blocks to a read and write data bus system to see whether or not any one of the test bits are inconsistent with the other test bits so that the parallel testing is carried out on various bit patterns.

Abstract: A level conversion output circuit includes two level conversion circuits for "high" and "low" logic signals, each of which includes a first CMOS inverter operating between an internal power supply of 3.3 V and ground, and a second CMOS inverter operating between an external power supply of 5 V and ground. One of the level conversion circuits is provided with an additional p-MOS transistor so that a 5.0 V voltage is applied to a gate of a p-MOS transistor of the second CMOS inverter from the external power supply through the additional p-MOS transistor, when the p-MOS transistor of the second CMOS inverter is controlled to be turned off.

Abstract: In a double word line type dynamic RAM, redundant memory cells to be substituted for defective cells are concentrated so as to form only one redundant sub-array in a row direction and in a column direction. The size of the redundant sub-array is made smaller than that of regular sub-arrays each composed of only regular cells. Although a minimum unit of cells to be replaced together becomes large in the double word line type dynamic RAM, the increase of the redundant memory cells can be effectively suppressed.

Abstract: A dynamic random access memory device selects a row of memory cells from a plurality of memory cell sub-arrays with main word lines and sub-word lines for a data access, and data bits read out from the row of memory cells are amplified by a sense amplifier circuit array, wherein a row block address decoder and a column block address decoder supply a first enable signal and a second enable signal to a row of memory cell sub-arrays and a column of memory cell sub-arrays so that only one of the sense amplifier circuit arrays is powered for the amplification, thereby decreasing peak current consumed by the sense amplifier circuit arrays.

Abstract: A dynamic RAM comprises first and second memory cell arrays respectively outputting holding data to corresponding bit lines when selected, sense amplifier means having amplifying MOS transistor for amplifying output of the bit lines of the first and second memory cell arrays, first and second transfer gate means respectively providing corresponding to the first and second memory cell arrays and controlling establishing and blocking connection between corresponding memory cell array and the sense amplifier means, first and second driver means respective provided corresponding to the first and second transfer gate means and generating gate control voltages for corresponding transfer gate means.

Abstract: A data bus selector/control amplifier comprises a plurality of basic circuit blocks for controlling the connection of the bus lines of a first data bus comprising a plurality of bus lines and a second data bus comprising a plurality of bus lines. The basic circuit blocks provided correspond to each of the bus lines of the second data bus. Each of the basic circuit blocks sends written data or precharging current to the second data bus via its own data amplifier. Second and third transfer gates retain the data to be written into and data to be read out from the data amplifier.

Abstract: A dynamic random access memory device is equipped with an internal power supply system for selectively distributing a step-down power voltage to internal component circuits, and the internal power supply system comprises a feedback loop for regulating the step-down power voltage on an internal power supply line to a reference voltage, a voltage detecting circuit monitoring an internal power voltage line to see whether or not the step-down power voltage is decayed to a critical level for producing a gate control signal, and an auxiliary variable load transistor coupled between the external power supply line and the internal power supply line and responsive to the gate control signal for supplementing current to the internal power supply line, wherein the critical level is inversely proportional to the external power voltage while the external power voltage is higher than the reference voltage, thereby preventing the step-down power voltage from undesirable overshoot upon production of the gate control signal.

Abstract: A plurality of data line pairs incorporated in a dynamic random access memory device extend over circuit components in parallel to a bit line pairs, and propagate a data bit between a read/write amplifier circuit and a sense amplifier unit shared between two memory cell blocks, wherein a column selector selectively charges one of the plurality of data line pairs before propagating the data bit so that a concentrated column selecting system and the data line pairs over the circuit components make the random access memory device possible to be fabricated on a relatively small semiconductor chip.

Abstract: A reference potential generating circuit includes a plurality of MOS field effect transistors and a reference potential driver circuit. The MOS field effect transistors have different threshold voltages and a reference potential is obtained by amplifying the threshold voltage difference of the MOS field effect transistors. During the period in which a power supply potential externally supplied is lower than a predetermined target value of the reference potential, the reference potential driver circuit drives an output terminal for producing a potential corresponding to the power supply potential supplied externally. In this reference potential generating circuit, the S/N ratio is good and the circuit operation is stable, and is effective for reducing the power consumption and for increasing the integration density in semiconductor integrated circuit devices.