Patents by Inventor Tadashi Maeda

Tadashi Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240282594
    Abstract: A disclosed method for manufacturing an electronic-component-mounted substrate includes: a step (i) of forming a temporary fixing film 13 in such a manner as to cover a plurality of solder precoats (11) formed on a plurality of lands (10b) on a substrate and an antioxidation film (12) formed in such a manner as to cover the solder precoats; a step (ii) of disposing a plurality of electronic components (30) on the plurality of solder precoats (11) via the antioxidation film (12) and the temporary fixing film (13); and a step (iii) of soldering the plurality of electronic components (30) to the plurality of lands (10b) by melting the plurality of solder precoats (11). The antioxidation film (12) contains a first thermoplastic resin. The temporary fixing film (13) contains an activating agent and a second thermoplastic resin. The softening point of the second thermoplastic resin is equal to or lower than the softening point of the first thermoplastic resin.
    Type: Application
    Filed: February 21, 2022
    Publication date: August 22, 2024
    Inventors: Tadashi MAEDA, Shingo OKAMURA, Yuki YOSHIOKA, Tadahiko SAKAI
  • Publication number: 20240268036
    Abstract: A disclosed method for manufacturing an electronic-component-mounted substrate includes: a step (i) of forming a temporary fixing film (13) in such a manner as to cover a plurality of solder precoats (11) formed on a plurality of lands (10b) on a substrate and an antioxidation film (12) formed in such a manner as to cover the solder precoats; a step (ii) of disposing a plurality of electronic components (30) on the plurality of solder precoats (11) via the antioxidation film (12) and the temporary fixing film (13); and a step (iii) of soldering the plurality of electronic components (30) to the lands (10b) by melting the plurality of solder precoats (11). The antioxidation film (12) contains a first thermoplastic resin. The temporary fixing film (13) contains an activating agent and a second thermoplastic resin. The softening point of the first thermoplastic resin is equal to or lower than the softening point of the second thermoplastic resin.
    Type: Application
    Filed: February 21, 2022
    Publication date: August 8, 2024
    Inventors: Shingo OKAMURA, Tadashi MAEDA, Yuki YOSHIOKA, Tadahiko SAKAI
  • Publication number: 20240196545
    Abstract: An adhesive for temporarily fixing an electronic component to a solder precoat covered at least partially with an organic film, the adhesive including a principal resin, and a solvent dissolving the principal resin. The content of the solvent is 25 mass % or more and 40 mass % or less, and the organic film dissolves in the solvent when the solder precoat is melted. According thereto, the formation of an oxide film on the surface of the solder precoat can be suppressed, and poor connection between the electrode having the solder precoat and the electronic component can be suppressed.
    Type: Application
    Filed: October 7, 2021
    Publication date: June 13, 2024
    Inventors: Yuki YOSHIOKA, Tadahiko SAKAI, Tadashi MAEDA, Shingo OKAMURA
  • Publication number: 20240015893
    Abstract: A mounting substrate manufacturing method for soldering a terminal of an electronic component to a land 2 of a substrate 1 includes: a paste disposing step of disposing a solder paste on the land 2; a melting and solidifying step of melting and solidifying the solder paste, to form a precoated area 3 coated with solder, on the land 2; a breaking step of breaking a residue covering a surface of the precoated area 3 by pressing a tool 432, 442 against the precoated area 3; a flux disposing step of disposing a flux F on the precoated area 3; a component placement step of placing an electronic component on the substrate 1, with the terminal of the electronic component aligned with the precoated area 3; and a reflow step of heating the substrate 1 to melt the precoated area 3, to solder the terminal to the land 2. This can provide a mounting substrate manufacturing method that can reduce the occurrence of soldering defects.
    Type: Application
    Filed: July 5, 2021
    Publication date: January 11, 2024
    Inventors: Masayuki MANTANI, Tadahiko SAKAI, Tadashi MAEDA, Yuki YOSHIOKA
  • Publication number: 20210328486
    Abstract: The unit coil is formed by: bending the coil end portions of the intermediate body such that, in a layer in which a length in an axial direction between the coil end portions is large, positions of the coil end portions projecting furthest from the accommodation portions in the axial direction move away from positions of the accommodation portions in the stacking direction, compared to the previous state; and aligning the positions, in the axial direction, of the coil end portions at an inner side of the annular shape, for each of the layers.
    Type: Application
    Filed: August 20, 2019
    Publication date: October 21, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yutaka HIROTA, Tadashi MAEDA, Takeshi YAGI
  • Patent number: 10168059
    Abstract: A filtering medium includes a nonwoven fabric and a first electrode having an input terminal of power. The first electrode is provided on a surface of the nonwoven fabric. Alternatively, in a case where the nonwoven fabric has a plurality of fiber layers, the first electrode may be provided between the fiber layers. An air purifier includes the filtering medium disposed between a sucker and a discharger of a gas, and an output terminal via which power is output to the first electrode of the filtering medium.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: January 1, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takayoshi Yamaguchi, Tadashi Maeda, Yosuke Wada
  • Patent number: 10115684
    Abstract: A semiconductor device includes a first semiconductor chip including a first plurality of wiring layers, and a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers, and a second semiconductor chip including a second plurality of wiring layers, a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers. The first semiconductor chip and the second semiconductor chip face each other via an insulation sheet. The first coil and the second coil are magnetically coupled with each other.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: October 30, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinpei Watanabe, Shinichi Uchida, Tadashi Maeda, Kazuo Henmi
  • Patent number: 9999123
    Abstract: A connection structure of circuit members includes a first circuit member, a second circuit member, and a joint portion. The first circuit member has a first main surface on which a light-transparent electrode is provided. The second circuit member has a second main surface on which a metal electrode is provided. The joint portion is interposed between the first main surface and the second main surface. The joint portion includes a resin portion and a solder portion. The solder portion electrically connects the light-transparent electrode and the metal electrode. The light-transparent electrode contains an oxide that includes indium and tin, and the solder portion contains bismuth and indium.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: June 12, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Arata Kishi, Tadashi Maeda, Tadahiko Sakai
  • Publication number: 20170148751
    Abstract: A semiconductor device includes a first semiconductor chip including a first plurality of wiring layers, and a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers, and a second semiconductor chip including a second plurality of wiring layers, a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers. The first semiconductor chip and the second semiconductor chip face each other via an insulation sheet. The first coil and the second coil are magnetically coupled with each other.
    Type: Application
    Filed: February 3, 2017
    Publication date: May 25, 2017
    Inventors: Shinpei WATANABE, Shinichi Uchida, Tadashi Maeda, Kazuo Henmi
  • Publication number: 20170072406
    Abstract: A filtering medium includes a nonwoven fabric and a first electrode having an input terminal of power. The first electrode is provided on a surface of the nonwoven fabric. Alternatively, in a case where the nonwoven fabric has a plurality of fiber layers, the first electrode may be provided between the fiber layers. An air purifier includes the filtering medium disposed between a sucker and a discharger of a gas, and an output terminal via which power is output to the first electrode of the filtering medium.
    Type: Application
    Filed: August 4, 2016
    Publication date: March 16, 2017
    Inventors: TAKAYOSHI YAMAGUCHI, TADASHI MAEDA, YOSUKE WADA
  • Patent number: 9589887
    Abstract: Dielectric breakdown is prevented between opposing two semiconductor chips, to improve the reliability of a semiconductor device. A first semiconductor chip has a wiring structure including a plurality of wiring layers, a first coil formed in the wiring structure, and an insulation film formed over the wiring structure. A second semiconductor chip has a wiring structure including a plurality of wiring layers, a second coil formed over the wiring structure, and an insulation film formed over the wiring structure. The first semiconductor chip and the second semiconductor chip are stacked via an insulation sheet with the insulation film of the first semiconductor chip and the insulation film of the second semiconductor chip facing each other. The first coil and the second coil are magnetically coupled with each other. Then, in each of the first and second semiconductor chips, wires and dummy wires are formed at the uppermost-layer wiring layer.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: March 7, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinpei Watanabe, Shinichi Uchida, Tadashi Maeda, Kazuo Henmi
  • Publication number: 20160316554
    Abstract: A connection structure of circuit members includes a first circuit member, a second circuit member, and a joint portion. The first circuit member has a first main surface on which a light-transparent electrode is provided. The second circuit member has a second main surface on which a metal electrode is provided. The joint portion is interposed between the first main surface and the second main surface. The joint portion includes a resin portion and a solder portion. The solder portion electrically connects the light-transparent electrode and the metal electrode. The light-transparent electrode contains an oxide that includes indium and tin, and the solder portion contains bismuth and indium.
    Type: Application
    Filed: March 18, 2016
    Publication date: October 27, 2016
    Inventors: ARATA KISHI, TADASHI MAEDA, TADAHIKO SAKAI
  • Patent number: 9466591
    Abstract: A semiconductor device includes a first semiconductor chip that includes a first main surface, a first inductor formed on the first main surface, and a first external connection terminal formed on the first main surface; a second semiconductor chip that includes a second main surface, a second inductor formed on the second main surface, a second external connection terminal formed on the second main surface; and a first insulating film that is located between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip overlap each other such that the first main surface and the second main face each other, the semiconductor device includes a facing region in which the first semiconductor chip and the second semiconductor chip overlap each other when seen in a plan view.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: October 11, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Shinpei Watanabe, Shinichi Uchida, Tadashi Maeda, Shigeru Tanaka
  • Patent number: 9439335
    Abstract: Disclosed is an electronic component mounting line on which a substrate undergoes solder paste printing, electronic component placements, and then reflow, while being moved from upstream to downstream.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: September 6, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tadashi Maeda, Hiroki Maruo, Tsubasa Saeki
  • Publication number: 20160118368
    Abstract: A semiconductor device includes a first semiconductor chip that includes a first main surface, a first inductor formed on the first main surface, and a first external connection terminal formed on the first main surface; a second semiconductor chip that includes a second main surface, a second inductor formed on the second main surface, a second external connection terminal formed on the second main surface; and a first insulating film that is located between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip overlap each other such that the first main surface and the second main face each other, the semiconductor device includes a facing region in which the first semiconductor chip and the second semiconductor chip overlap each other when seen in a plan view.
    Type: Application
    Filed: January 6, 2016
    Publication date: April 28, 2016
    Inventors: Shinpei WATANABE, Shinichi UCHIDA, Tadashi MAEDA, Shigeru TANAKA
  • Publication number: 20160093570
    Abstract: Dielectric breakdown is prevented between opposing two semiconductor chips, to improve the reliability of a semiconductor device. A first semiconductor chip has a wiring structure including a plurality of wiring layers, a first coil formed in the wiring structure, and an insulation film formed over the wiring structure. A second semiconductor chip has a wiring structure including a plurality of wiring layers, a second coil formed over the wiring structure, and an insulation film formed over the wiring structure. The first semiconductor chip and the second semiconductor chip are stacked via an insulation sheet with the insulation film of the first semiconductor chip and the insulation film of the second semiconductor chip facing each other. The first coil and the second coil are magnetically coupled with each other. Then, in each of the first and second semiconductor chips, wires and dummy wires are formed at the uppermost-layer wiring layer.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 31, 2016
    Inventors: Shinpei WATANABE, Shinichi UCHIDA, Tadashi MAEDA, Kazuo HENMI
  • Patent number: 9252200
    Abstract: In a first semiconductor chip, a first multilayer interconnect layer is formed on a first substrate, and a first inductor is formed in the first multilayer interconnect layer. In a second semiconductor chip, a second multilayer interconnect layer is formed on a second substrate. A second inductor is formed in the second multilayer interconnect layer. The first semiconductor chip and the second semiconductor chip overlap each other in a direction in which the first multilayer interconnect layer and the second multilayer interconnect layer face each other. In addition, the first inductor and the second inductor overlap each other when seen in a plan view. At least one end of a first insulating film does not overlap the end of a facing region, in a Y direction.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: February 2, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinpei Watanabe, Shinichi Uchida, Tadashi Maeda, Shigeru Tanaka
  • Patent number: 9125329
    Abstract: Disclosed is an electronic component mounting line on which a substrate undergoes solder paste printing, electronic component placements, and then reflow, while being moved from upstream to downstream. The line includes: a substrate feeding machine for feeding the substrate; a screen printing machine for applying solder paste to the substrate; a first electronic component placement machine for placing a first electronic component on the substrate; a resin dispensing machine for dispensing a thermosetting resin onto at least one reinforcement position arranged on the substrate; a second electronic component placement machine for placing a second electronic component on the substrate, such that its peripheral edge portion comes in contact with the thermosetting resin; and a reflow machine for bonding the first and second electronic components to the substrate, by heating and cooling the resultant.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: September 1, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tadashi Maeda, Hiroki Maruo, Tsubasa Saeki
  • Publication number: 20150130022
    Abstract: In a first semiconductor chip, a first multilayer interconnect layer is formed on a first substrate, and a first inductor is formed in the first multilayer interconnect layer. In a second semiconductor chip, a second multilayer interconnect layer is formed on a second substrate. A second inductor is formed in the second multilayer interconnect layer. The first semiconductor chip and the second semiconductor chip overlap each other in a direction in which the first multilayer interconnect layer and the second multilayer interconnect layer face each other. In addition, the first inductor and the second inductor overlap each other when seen in a plan view. At least one end of a first insulating film does not overlap the end of a facing region, in a Y direction.
    Type: Application
    Filed: October 23, 2014
    Publication date: May 14, 2015
    Inventors: Shinpei Watanabe, Shinichi Uchida, Tadashi Maeda, Shigeru Tanaka
  • Patent number: 9030064
    Abstract: The totally-enclosed fan-cooled motor includes the stator; the rotor; the drive side bracket; the counter drive side bracket; a pair of the bearings; the external fan that sends cooling air to the stator; the internal fan; the heat radiator that is arranged on an outer side of the drive side bracket and is mounted on the rotation shaft; the cover that contains a joint, which connects the rotation shaft extending to an outer side of the drive side bracket of the motor and a reduction gear, and is provided in parallel with the joint; and the ventilation path that is arranged between the drive side bracket and an end of the cover, and includes the outlet causes the cooling air induced by rotation of the heat radiator to flow to the heat radiator and discharges the cooling air outside the motor.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: May 12, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Seiji Haga, Kazuto Minagawa, Tadashi Maeda