Abstract: A semiconductor integrated circuit having a field effect transistor formed on a compound semiconductor is disclosed, that comprises a first power supply, a second power supply for supplying a voltage lower than a voltage that the first power supplies, and at least one virtual power supply that is not connected to the outside and that has a voltage between the voltage of the first power supply and the voltage of the second power supply, wherein the number of the virtual power supplies is designated to a value larger than the quotient of which the voltage between the first power supply and the second power supply is divided by the forward turn-on voltage of a gate electrode of the field effect transistor. In the case that a signal received from a circuit with a low voltage is connected to a circuit between any power supply, the signal is received by a directly coupled logic circuit with a depletion type field effect transistor as a drive circuit.

Abstract: The invention provides a logic circuit including (a) a load element having ends one of which is electrically connected to a first terminal of a voltage source, and the other to an output terminal, (b) a first enhancement mode FET including a drain electrode electrically connected to the output terminal, a gate electrode connected to an input terminal, and a source electrode connected to a junction, (c) a second enhancement mode FET including a drain electrode electrically connected to the first terminal, a gate electrode connected to the output terminal, and a source electrode connected to the junction, and (d) a depletion mode FET including a drain electrode electrically connected to the junction, a gate electrode connected to a control terminal, and a source electrode connected to a second terminal of the voltage source. The logic circuit ensures sufficient noise margin to temperature variation, resulting in a lower supply voltage.

Abstract: In a switching speed fluctuation detecting apparatus, an input terminal for receiving a signal having a definite time period, a series arrangement of at least one first logic circuit connected to the input terminal, a second logic circuit having a first input connected to the input terminal and a second input connected to an output of the series arrangement and an integrator connected to an output of the second logic circuit are provided.

Abstract: A cell analyzing system flows a liquid to be tested and a sheath liquid through a flattened flow passage. An image of the flattened flow passage is formed at two different magnifications. The thickness of the liquid to be tested in the flattened flow passage is changed between the two different magnifications to maintain this thickness at a value smaller than a depth of field of the apparatus forming the image. The thickness of the liquid to be tested is changed by changing its flow relationship to the sheath liquid.

Abstract: A cell analyzing system flows a liquid to be tested and a sheath liquid through a flattened flow passage. An image of the flattened flow passage is formed at two different magnifications. The thickness of the liquid to be tested in the flattened flow passage is changed between the two different magnifications to maintain this thickness at a value smaller than a depth of field of the apparatus forming the image. The thickness of the liquid to be tested is changed by changing its flow relationship to the sheath liquid.