Patents by Inventor Tadashi Nishimura

Tadashi Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10316692
    Abstract: A method of suppressing shaft vibration of a turbocharger capable of being driven by a motor includes: a specific-vibration-state determination step of determining whether a rotor shaft of the turbocharger is in a specific vibration state in which a magnitude of shaft vibration of the rotor shaft is, or is likely to be, greater than a predetermined magnitude; an excited state determination step of determining whether the motor is in an excited state in which an exciting voltage is applied to the motor; and a vibration suppression execution step of applying the exciting voltage to the motor if it is determined that the rotor shaft is in the specific vibration state in the specific-vibration-state determination step and it is determined that the motor is not in the excited state in the excited state determination step.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: June 11, 2019
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Tadashi Yoshida, Musashi Sakamoto, Ryoji Sasaki, Yoshihisa Ono, Hidetaka Nishimura, Takeshi Tsuji
  • Patent number: 10093075
    Abstract: A method for manufacturing a structure in which an edge portion of the structure formed by stacking a plurality of members is friction stir welded. The manufacturing method includes: a welding step of forming a friction stir welded portion by bringing a friction stir welding tool from a side of a surface of a member on one side into contact with a superposition portion of works in which the members are stacked while rotating the friction stir welding tool; and a cutting step of cutting the friction stir welded portion, and in each of two or more works produced by the cutting, a welded portion of the edge portion of the structure is formed with the cut friction stir welded portion.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: October 9, 2018
    Assignee: ISEL CO., LTD.
    Inventors: Noboru Mochizuki, Tadashi Nishimura
  • Publication number: 20160129670
    Abstract: A method for manufacturing a structure in which an edge portion of the structure formed by stacking a plurality of members is friction stir welded. The manufacturing method includes: a welding step of foaming a friction stir welded portion by bringing a friction stir welding tool from a side of a surface of a member on one side into contact with a superposition portion of works in which the members are stacked while rotating the friction stir welding tool; and a cutting step of cutting the friction stir welded portion, and in each of two or more works produced by the cutting, a welded portion of the edge portion of the structure is formed with the cut friction stir welded portion.
    Type: Application
    Filed: December 28, 2015
    Publication date: May 12, 2016
    Inventors: Noboru MOCHIZUKI, Tadashi NISHIMURA
  • Patent number: 9084305
    Abstract: A lighting system includes a lighting load and a lighting control device. The lighting control device is configured to adjust a light output of the lighting load to a first light output corresponding to a first correlated color temperature and a first illuminance in a first time slot, and to decrease the light output of the lighting load up to a second light output corresponding to a second correlated color temperature and a second illuminance with the passage of time in a second time slot after the first time slot.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: July 14, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Naohiro Toda, Hiroki Noguchi, Tadashi Nishimura, Shinsuke Nishioka, Toshikazu Kawashima
  • Publication number: 20130229113
    Abstract: A lighting system includes a lighting load and a lighting control device. The lighting control device is configured to adjust a light output of the lighting load to a first light output corresponding to a first correlated color temperature and a first illuminance in a first time slot, and to decrease the light output of the lighting load up to a second light output corresponding to a second correlated color temperature and a second illuminance with the passage of time in a second time slot after the first time slot.
    Type: Application
    Filed: February 6, 2013
    Publication date: September 5, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Naohiro TODA, Hiroki NOGUCHI, Tadashi NISHIMURA, Shinsuke NISHIOKA, Toshikazu KAWASHIMA
  • Patent number: 8118347
    Abstract: An aspect in accordance with the present invention is a structure of mounting an impact absorption material for use with a vehicle. The structure includes: a door trim 30, a holder, and an EA pad. The holder includes a base and a plurality of legs, the base of the holder being disposed on the compartment outer side surface of the EA pad. The plurality of legs are disposed at intervals around an outer peripheral edge of the base of the holder and extend from the base of the holder, along an outer peripheral side surface of the EA pad, and to the door trim, thereby fixing the base of the holder to the door trim.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: February 21, 2012
    Assignees: Toyota Boshoku Kabushiki Kaisha, Hayashi Telempu Co., Ltd.
    Inventors: Akihiro Kawashima, Masami Uratsu, Michinori Kawasumi, Eiji Fujii, Tomonari Masuda, Tadashi Nishimura, Mariko Wada, Mamoru Yamaguchi, Kenichi Uemori
  • Publication number: 20100308621
    Abstract: An aspect in accordance with the present invention is a structure of mounting an impact absorption material for use with a vehicle. The structure includes: a door trim 30, a holder, and an EA pad. The holder includes a base and a plurality of legs, the base of the holder being disposed on the compartment outer side surface of the EA pad. The plurality of legs are disposed at intervals around an outer peripheral edge of the base of the holder and extend from the base of the holder, along an outer peripheral side surface of the EA pad, and to the door trim, thereby fixing the base of the holder to the door trim.
    Type: Application
    Filed: June 2, 2010
    Publication date: December 9, 2010
    Applicants: TOYOTA BOSHOKU KABUSHIKI KAISHA, HAYASHI TELEMPU CO., LTD.
    Inventors: Akihiro Kawashima, Masami Uratsu, Michinori Kawasumi, Eiji Fujii, Tomonari Masuda, Tadashi Nishimura, Mariko Wada, Mamoru Yamaguchi, Kenichi Uemori
  • Publication number: 20040135211
    Abstract: According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.
    Type: Application
    Filed: December 24, 2003
    Publication date: July 15, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Yasuo Inoue, Tadashi Nishimura, Yasuo Yamaguchi, Toshiaki Iwamatsu
  • Patent number: 6727552
    Abstract: According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: April 27, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Inoue, Tadashi Nishimura, Yasuo Yamaguchi, Toshiaki Iwamatsu
  • Patent number: 6649976
    Abstract: A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: November 18, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiaki Iwamatsu, Yasuo Inoue, Yasuo Yamaguchi, Tadashi Nishimura
  • Patent number: 6459125
    Abstract: A semiconductor device for CSP mounting which avoids errors due to alpha rays and is highly stress-resistant is provided. A buried oxide film (107) is formed on a semiconductor substrate (101), and a MOS transistor having an SOI structure is formed on the buried oxide film (107). The MOS transistor comprises source and drain regions (120a, 120b) formed in a semiconductor layer (120), and a gate electrode (110). An aluminum pad (103) connected to any one of the source and drain regions (120a, 120b) through a connecting mechanism not shown, and a silicon nitride film (104) having an opening on the top of the aluminum pad (103) are formed on an interlayer insulation film (108). A layer of titanium (105) and a layer of nickel (106) are formed extending from the aluminum pad (103) to an end of the silicon nitride film (104). A solder bump (11) is disposed on the layer of nickel (106).
    Type: Grant
    Filed: July 27, 1998
    Date of Patent: October 1, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigenobu Maeda, Tadashi Nishimura, Kazuhito Tsutsumi, Shigeto Maegawa, Yuuichi Hirano
  • Publication number: 20020110954
    Abstract: A semiconductor device for CSP mounting which avoids errors due to alpha rays and is highly stress-resistant is provided. A buried oxide film (107) is formed on a semiconductor substrate (101), and a MOS transistor having an SOI structure is formed on the buried oxide film (107). The MOS transistor comprises source and drain regions (120a, 120b) formed in a semiconductor layer (120), and a gate electrode (110). An aluminum pad (103) connected to any one of the source and drain regions (120a, 120b) through a connecting mechanism not shown, and a silicon nitride film (104) having an opening on the top of the aluminum pad (103) are formed on an interlayer insulation film (108). A layer of titanium (105) and a layer of nickel (106) are formed extending from the aluminum pad (103) to an end of the silicon nitride film (104). A solder bump (11) is disposed on the layer of nickel (106).
    Type: Application
    Filed: April 16, 2002
    Publication date: August 15, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Shigenobu Maeda, Tadashi Nishimura, Kazuhito Tsutsumi, Shigeto Maegawa, Yuuichi Hirano
  • Publication number: 20020105031
    Abstract: According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.
    Type: Application
    Filed: February 5, 2002
    Publication date: August 8, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Yasuo Inoue, Tadashi Nishimura, Yasuo Yamaguchi, Toshiaki Iwamatsu
  • Publication number: 20020048919
    Abstract: A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.
    Type: Application
    Filed: October 22, 2001
    Publication date: April 25, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Toshiaki Iwamatsu, Yasuo Inoue, Yasuo Yamaguchi, Tadashi Nishimura
  • Patent number: 6358783
    Abstract: A semiconductor device includes a MOS-type field effect transistor (SOI-MOSFET) formed on a thin silicon layer on an insulator layer. The SOI-MOSFET has a gate overlap-type LDD structure in which additional source/drain regions having an impurity concentration of 3×1017 to 3×1018/cm3 overlapping with a gate electrode are provided in the silicon layer. According to this structure, when the SOI-MOSFET is on operation, only the additional source/drain regions are depleted, so that it is possible to obtain satisfactory transistor characteristics. Additional source/drain regions in this structure are formed by combination of vertical ion implantation using the gate electrode as a mask and thermal diffusion or oblique ion implantation using the gate electrode as a mask.
    Type: Grant
    Filed: January 20, 1999
    Date of Patent: March 19, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Yamaguchi, Tadashi Nishimura
  • Patent number: 6351014
    Abstract: According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.
    Type: Grant
    Filed: March 6, 2000
    Date of Patent: February 26, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Inoue, Tadashi Nishimura, Yasuo Yamaguchi, Toshiaki Iwamatsu
  • Publication number: 20020005552
    Abstract: According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.
    Type: Application
    Filed: March 6, 2000
    Publication date: January 17, 2002
    Inventors: Yasuo Inoue, Tadashi Nishimura, Yasuo Yamaguchi, Toshiaki Iwamatsu
  • Publication number: 20020003259
    Abstract: A semiconductor device for CSP mounting which avoids errors due to alpha rays and is highly stress-resistant is provided. A buried oxide film (107) is formed on a semiconductor substrate (101), and a MOS transistor having an SOI structure is formed on the buried oxide film (107). The MOS transistor comprises source and drain regions (120a, 120b) formed in a semiconductor layer (120), and a gate electrode (110). An aluminum pad (103) connected to any one of the source and drain regions (120a, 120b) through a connecting mechanism not shown, and a silicon nitride film (104) having an opening on the top of the aluminum pad (103) are formed on an interlayer insulation film (108). A layer of titanium (105) and a layer of nickel (106) are formed extending from the aluminum pad (103) to an end of the silicon nitride film (104). A solder bump (11) is disposed on the layer of nickel (106).
    Type: Application
    Filed: July 27, 1998
    Publication date: January 10, 2002
    Inventors: SHIGENOBU MAEDA, TADASHI NISHIMURA, KAZUHITO TSUTSUMI, SHIGETO MAEGAWA, YUUICHI HIRANO
  • Patent number: 6319805
    Abstract: A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.
    Type: Grant
    Filed: February 8, 2000
    Date of Patent: November 20, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiaki Iwamatsu, Yasuo Inoue, Yasuo Yamaguchi, Tadashi Nishimura
  • Patent number: 6214664
    Abstract: In a semiconductor device and a method of manufacturing the same, an isolating and insulating film is provided at an end neighboring to a second impurity region with a groove extended to a semiconductor substrate. This removes a crystal defect existed at the end of the isolating and insulating film, and thus prevents leak of a current at this portion from a storage node. Consequently, provision of the groove at the edge portion of the isolating oxide film neighboring to the impurity region removes a crystal defect at this region, and thus eliminates a possibility of leak of a current.
    Type: Grant
    Filed: November 18, 1999
    Date of Patent: April 10, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Kimura, Tadashi Nishimura, Takahiro Tsuruda, Kazutami Arimoto, Tadato Yamagata, Kazuyasu Fujishima