Abstract: A semiconductor device includes a conductor layer (3, 7) having a silicon crystal, an insulator layer (5, 15) formed on the surface of the conductor layer (3, 7) having a contact hole therethrough to said surface of the conductor layer (3, 7), an interconnecting portion formed at a predetermined location in the insulator layer (5, 15) and having a contact hole (6, 9) the bottom surface of which becomes the surface of the conductor layer (3, 7), a barrier layer (14) formed at the bottom of said contact hole at least on the surface of the conductor layer (3, 7) in the interconnecting portion, and a metal silicide layer (12) formed on the barrier layer (14).

Abstract: The present invention provides a three-dimensional shape measuring device and a sensor employed for the three-dimensional shape measuring device.

Abstract: Disclosed herein is a process for producing a single crystal layer of a semiconductor device, which comprises the steps of providing an oxide insulator layer separated by an opening part for seeding, on a major surface of a single crystal semiconductor substrate of the cubic system, providing a polycrystalline or amorphous semiconductor layer on the entire surface of the insulator layer inclusive of the opening part, then providing a protective layer comprising at least a reflective or anti-reflection film comprising stripes of a predetermined width, in a predetermined direction relative to the opening part and at a predetermined interval, the protective layer capable of controlling the temperature distributions in the semiconductor layer at the parts corresponding to the stripes or the parts not corresponding to the stripes, thereby completing a base for producing a semiconductor device, thereafter the surface of the base is irradiated with an energy beam through the striped reflective or anti-reflection fil

Abstract: A laser beam irradiating apparatus is capable of laser annealing with high precision and uniform over the entire surface of a sample. Luminous flux of the laser beam output from a laser source is expanded by a beam expander. The power of the laser beam which has passed through the beam expander is adjusted by a half-wave plate of synthetic quarts and a polarizing prism of synthetic quarts. The laser beam emitted from polarizing prism is guided to a prescribed position by mirrors, and swung in the direction of the X-axis by an X-axis rotation mirror. The laser beam reflected from X-axis rotation mirror has its diameter reduced by a f-.theta. lens to have a prescribed beam spot diameter on the surface of a silicon wafer, and laser beam scanning is carried out at a constant speed.

Abstract: A knowledge base management system and method for managing a knowledge base system which includes a primary data storage section storing received primary data. A change registration section records change data indicating which of the primary data has been changed. A data conversion section converts the primary data into secondary data which has a data format compatible with the knowledge base system. A knowledge base section has a secondary data storage section which stores the secondary data, and a reasoning calculation section accesses the secondary data based on a received retrieval inquiry. A knowledge management section controls the conversion section.

Abstract: An MOS field effect transistor comprises a channel region (6) of a first conductivity type formed in a semiconductor layer (3) on an insulator substrate (2), a source region (8) and a drain region (9) of a second conductivity type formed in contact with one and the other sides of the channel region (6) in the semiconductor layer (3), respectively, a body region (7) formed in contact with at least a part of the channel region (6) and a part of a periphery of the source region (8) in the semiconductor layer (3) and having a higher impurity concentration than that of the channel region (6), a gate electric thin film (4) and a gate electrode (5) formed on the channel region (6), and a conductor (14a) connected in common to the source region (8) and the body region (7).

Abstract: Disclosed herein is a semiconductor pressure sensor which can improve a withstand voltage across piezoresistance and interconnection layers and a semiconductor substrate. In this semiconductor pressure sensor, a plurality of dot seeds, which are regions for serving as seed crystals for growing monocrystals, are arranged to enclose the piezoresistance, and the interconnection layer is formed to pass through a clearance between adjacent ones of the dot seeds.

Abstract: An upper insulating layer is formed on an upper surface of a gate electrode formed on an insulating substrate. A gate insulating layer is formed on sidewalls of the gate electrode and the surfaces of the upper insulating layer. A semiconductor layer is formed on the surfaces of the gate insulating layer. Three source/drain regions are formed in the semiconductor layer. Two independent channel regions are formed in the semiconductor layer along both side surfaces of the gate electrode. Source/drain regions are arranged on both ends of two channel regions. Each source/drain region has an LDD structure formed in a self alignment manner by an oblique ion implantation method and a vertical ion implantation method using sidewall insulating layers formed on the channel regions as masks.

Abstract: A stacked semiconductor device has three-dimensional alternate layers of iconductor elements and insulating layers each electrically insulating the adjacent upper and lower layers of semiconductor elements, formed on a single crystal semiconductor substrate. A semiconductor is deposited in openings formed respectively in the insulating layers to form single crystal semiconductor layers each having the same crystal axis as the single crystal semiconductor substrate respectively over the insulating layers, and semiconductor elements are formed respectively in a plurality of layers. The opening formed through the upper insulating layer reaches the lower layer of the semiconductor element immediately below the same upper insulating layer, and is formed at a position spaced apart horizontally from the opening formed through the lower insulating layer immediately below the same upper insulating layer.

Abstract: An MOS field effect transistor comprises a channel region (6) of a first conductivity type formed in a semiconductor layer (3) on an insulator substrate (2), a source region (8) and a drain region (9) of a second conductivity type formed in contact with one and the other sides of the channel region (6) in the semiconductor layer (3), respectively, a body region (7) formed in contact with at least a part of the channel region (6) and a part of a periphery of the source region (8) in the semiconductor layer (3) and having a higher impurity concentration than that of the channel region (6), a gate electric thin film (4) and a gate electrode (5) formed on the channel region (6), and a conductor (14a) connected in common to the source region (8) and the body region (7).

Abstract: A wafer structure for forming a semiconductor single crystal film comprises a semiconductor single crystal substrate, a plurality of recesses formed in a grooved shape to one main surface of the semiconductor single crystal substrate, insulation material embedded to the inside of these recesses, an insulation layer deposited over the insulation material and the semiconductor single crystal substrate and integrated with the insulation material and a polycrystalline or amorphous semiconductor layer to be recrystallized disposed over the insulation layer.A wafer structure with no or less grain boundaries can be obtained. Further, polycrystalline or amorphous semiconductor layer can be prevented from peeling off the substrate by the additional layering of a protecting insulation layer.

Abstract: A field effect transistor comprises source, drain and channel regions in a semiconductor layer formed on an insulating substrate. An island-shaped semiconductor layer of a first conductivity type is formed on a major surface of the insulating substrate and isolated from the surroundings. Source and drain regions of a second conductivity type are formed spaced apart from each other in the island-shaped semiconductor layer so as to define the channel region having a part of a major surface of the island-shaped semiconductor layer as a channel surface. A gate electrode is formed on the channel surface through an insulating film. A sidewall insulating film is formed on a sidewall of other region than the source region in the island-shaped semiconductor layer. A semiconductor sidewall layer of the first conductivity type is formed on a sidewall of the island-shaped semiconductor layer corresponding to the source region and the sidewall insulating film.

Abstract: A vertical MOS transistor having its channel length determined by the thickness of an insulating layer provided over a semiconductor substrate, rather than by the depth of a trench in which the transistor is formed. As a result, the characteristics of the transistor as relatively unaffected by doping and heat-treatment steps which are performed during formation. Also, the transistor may be formed so as to occupy very little surface area, making it suitable for application in high-density DRAMs.

Abstract: A stacked static random access memory SRAM having a plurality of memory cells is disclosed. Individual memory cell has a portion formed in an upper active element layer in the device structure and a portion formed in a lower active element layer in the device structure separated from the upper layer by an intermediate insulating layer. A word line, a bit line and access transistors are formed in the same upper active element layer, eliminating the need for interconnecting them through the insulating layer. The elimination of the inter-layer connections helps to reduce the number of through-holes required to be made in the insulating layer. This in turn reduces the area to be occupied by the memory cell and leads to a simplified manufacturing process of the SRAM.

Abstract: Disclosed is an apparatus for detecting the three-dimensional configuration of an object employing an optical cutting method. A light projector pulse-flashes slit-shaped light and causes the light to scan an object at a predetermined speed. An image sensor having a plurality of pixels is disposed in opposition to the object. An optical system forms on the image sensor an image of an optical cutting line formed on the surface of the object by the light. A difference detector detects the difference between the on- and off- levels of each of pulses of the image detected by the pixels of the sensor. A time calculator calculates the time at which the image has passed each of the pixels, on the basis of the difference detected by the difference detector. A configuration calculator calculates the three-dimensional configuration of the object on the basis of the calculated passage time and the scanning speed of the slit-shaped light.

Abstract: An improved method of manufacturing semiconductor devices having a stacked structure is disclosed. A p-channel semiconductor substrate is prepared, and on the major surface of the substrate, n-channel source and drain regions and a gate electrode are formed to provide a n-channel transistor. Sidewalls are formed of P type single-crystal silicon on the opposite size of the gate electrode of n-channel transistor with an insulating layer interposed between the sidewalls and the gate electrode. A single-crystal layer covers the source, drain and gate electrode of the n-channel transistor and the sidewall structures. A P type impurity present in the sidewalls is diffused into the single-crystal layer.

Abstract: A thin film semiconductor device is formed by preparing a substrate, forming a pattern of metal thin film on the substrate, forming an insulating layer on the metal thin film, and forming a pattern of a semiconductor thin film active layer over the pattern of the metal thin film by laser CVD.

Abstract: Oxygen ions or nitrogen ions are implanted into a semiconductor substrate to form a dielectric layer in the semiconductor substrate. An epitaxial semiconductor layer of at least 2 .mu.m in thickness, having excellent reproducibility and good crystallinity, is formed on a residual semiconductor layer on the dielectric layer by epitaxial growth, to serve as a region for forming semiconductor elements. Thus, a semiconductor device having high isolation breakdown voltage is impemented.Further, both oxygen ions and nitrogen ions are respectively implanted into a portions of a semiconductor substrate, which are adjacent to each other along the direction of thickness, to form two dielectric layers. Thus, a semiconductor device having higher isolation breakdown voltage is implemented.

Abstract: A semiconductor memory has a first insulating layer formed on one major surface of a silicon single crystal substrate having a hole portion. The hole portion is filled with a material of a first conductivity type up to the depth of the first insulating layer. A first single crystal silicon layer is formed on the first insulating layer and a diffused region of the first single crystal silicon layer is formed on the first insulating layer and on the material of a first conductivity type. Source and drain regions are formed by doping the first single crystal silicon layer with a first impurity up to high degree of concentration. A second insulating layer is then formed on the first single crystal silicon layer with a low resistive portion formed on this second insulating layer to form source and drain regions. A second single crystal silicon layer is formed along the wall surfaces of the second insulating layer and the low resistive portion.

Abstract: In a method of manufacturing a semiconductor device comprising melting an amorphous or polycrystalline first semiconductor layer formed on the surface of a first dielectric layer by irradiating energy rays thereon, and converting the same into single crystals by the subsequent lowering of the temperature and forming a second dielectric layer and a second semiconductor layer on the first semiconductor layer. Energy rays are irradiated under the condition capable of melting the first semiconductor layer through the second semiconductor layer and the second dielectric layer and, after the completion of the conversion into single crystals, the second semiconductor layer and the second dielectric layer are eliminated through etching.