Patents by Inventor Tadashi Nishimura

Tadashi Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4861418
    Abstract: A method of manufacturing a semiconductor crystalline layer comprising the following steps: a step of forming, on a single crystalline substrate composed of a semiconductor having a main face on <001> face and having a diamond-type crystal structure, an orientation flat face in which the direction of the intersection with the main face makes a predetermined angle relative to the direction <110> on the main face and which serves as a reference for defining the direction of arranging semiconductor chips formed on the substrate; a step of forming, on the main face of the substrate, an insulation layer at least a portion of which has an opening reaching the main face and which insulates the substrate at the region other than the opening; a step of forming a semiconductor layer composed of a polycrystalline or amorphous semiconductor on the surface of the opening and the insulation layer; a step of forming a reflectivity varying layer which is in the direction in parallel with or vertical to the inters
    Type: Grant
    Filed: March 6, 1987
    Date of Patent: August 29, 1989
    Assignee: Kozo Iizuka, Director General, Agency of Industrial Science and Technology
    Inventors: Tadashi Nishimura, Yasuo Inoue, Kazuyuki Sugahara, Shigeru Kusunoki
  • Patent number: 4845537
    Abstract: A vertical MOS transistor having its channel length determined by the thickness of an insulating layer provided over a semiconductor substrate, rather than by the depth of a trench in which the transistor is formed. As a result, the characteristics of the transistor as relatively unaffected by doping and heat-treatment steps which are performed during formation. Also, the transistor may be formed so as to occupy very little surface area, making it suitable for application in high-density DRAMs.
    Type: Grant
    Filed: December 1, 1987
    Date of Patent: July 4, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tadashi Nishimura, Kazuyuki Sugahara, Shigeru Kusunoki, Akihiko Ohsaki
  • Patent number: 4822752
    Abstract: Disclosed herein is a process for producing a single crystal layer of a semiconductor device, which comprises the steps of providing an oxide insulator layer separated by an opening part for seeding, on a major surface of a single crystal semiconductor substrate of the cubic system, providing a polycrystalline or amorphous semiconductor layer on the entire surface of the insulator layer inclusive of the opening part, then providing a protective layer comprising at least a reflective or anti-reflection film comprising strips of a predetermined width, in a predetermined direction relative to the opening part and at a predetermined interval, the protective layer capable of controlling the temperature distributions in the semiconductor layer at the parts corresponding to the stripes or the parts not corresponding to the stripes, thereby completing a base for producing a semiconductor device, thereafter the surface of the base is irradiated with an energy beam through the striped reflective or anti-reflection film
    Type: Grant
    Filed: March 6, 1987
    Date of Patent: April 18, 1989
    Assignee: Agency of Industrial Science and Technology
    Inventors: Kazuyuki Sugahara, Tadashi Nishimura, Shigeru Kusunoki, Yasuo Inoue
  • Patent number: 4822751
    Abstract: A thin film semiconductor device is formed by preparing a substrate, forming a pattern of metal thin film on the substrate, forming an insulating layer on the metal thin film, and forming a pattern of a semiconductor thin film active layer, which is self-aligned to the pattern of the metal thin film, by laser CVD.
    Type: Grant
    Filed: March 31, 1987
    Date of Patent: April 18, 1989
    Assignee: Mitsubishi Denki Kabushi Kaisha
    Inventors: Akira Ishizu, Tadashi Nishimura, Yasuo Inoue
  • Patent number: 4797723
    Abstract: A stacked semiconductor device includes a first integrated circuit formed on the principal surface of a semiconductor layer and containing active elements, and a second integrated circuit formed on the first integrated circuit through an insulation layer and containing active elements. The second integrated circuit is formed on that part of the surface of the first integrated circuit which is exclusive of selected active elements, to establish an open space for heat dissipation.
    Type: Grant
    Filed: September 8, 1987
    Date of Patent: January 10, 1989
    Assignee: Mitsubishi Denki, K.K.
    Inventors: Tadashi Nishimura, Yoichi Akasaka
  • Patent number: 4787740
    Abstract: An apparatus for determining crystal orientation comprises: a polarizer for polarizing an incident light beam; a polarization analyzer for selecting light having a selected polarization direction in Raman scattered light; and a synchronizer for enabling synchronous rotations of the polarizer and the polarization analyzer.
    Type: Grant
    Filed: February 5, 1987
    Date of Patent: November 29, 1988
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Inoue, Tadashi Nishimura, Kazuyuki Sugahara, Shigeru Kusunoki
  • Patent number: 4778269
    Abstract: In a method for determining orientation of a crystal with polarization selective Raman microprobe spectroscopy, polarization angles of both light incident on the crystal and Raman scattered light emitted from the crystal are varied coincidently in ordinary circumstances and only either one of the polarization angles is varied in only case that intensity of the scattered beam does not change substantially in spite of the coincident variation of both the polarization angles.
    Type: Grant
    Filed: February 6, 1987
    Date of Patent: October 18, 1988
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Inoue, Tadashi Nishimura, Kazuyuki Sugahara, Shigeru Kusunoki
  • Patent number: 4714684
    Abstract: In a method of manufacturing a semiconductor device of a three-dimensional structure having a semiconductor substrate and another single crystal semiconductor layer formed thereon, the another single crystal semiconductor layer is prepared by melting a vapor-deposited amorphous or polycrystalline semiconductor layer by the energy of laser beams then solidifying and converting the layer into single crystals. For initiating the melting at selected regions of the layer, the layer is formed at the surface thereof with a silicon nitride film of a uniform thickness and a silicon nitride film with a thickness at the region corresponding to the selected region different from that of the remaining region. The region thicker or thinner than other region reflects the laser energy at different reflectivity thereby to provide a desired temperature distribution.
    Type: Grant
    Filed: March 26, 1986
    Date of Patent: December 22, 1987
    Assignee: Agency of Industrial Science and Technology
    Inventors: Kazuyuki Sugahara, Tadashi Nishimura, Shigeru Kusunoki, Yasuo Inoue
  • Patent number: 4694143
    Abstract: A zone melting apparatus, in accordance with the present invention for monocrystallizing a semiconductor layer in a layered substance, includes: an upper elongated heater for zone melting of the semiconductor layer, the upper heater being disposed above and parallel to the semiconductor layer; a plurality of lower elongated heaters for heating the whole layered substance, the lower heaters being disposed in a plane below and parallel to the layered substance and the axis of each of the lower heaters being substantially perpendicular to the axis of the upper heater; a plurality of power suppliers for supplying electric power to the lower heaters; one or more temperature sensors for estimating the temperature of the layered substance; and a controller for controlling the power suppliers in response to the output of the temperature sensor(s), the controller making control so that the temperature of the central portion of the layered substance is slightly lower than that of the outer portions thereof.
    Type: Grant
    Filed: December 31, 1985
    Date of Patent: September 15, 1987
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tadashi Nishimura, Kazuyuki Sugahara, Shigeru Kusunoki, Yasuo Inoue
  • Patent number: 4661167
    Abstract: A method for manufacturing a semiconductor device, which comprises: a first process for producing a semiconductor layer of polycrystalline silicon or amorphous silicon on the surface of a substrate of insulator or a substrate made up by forming an insulating layer on a basic semiconductor; a second process for producing an island of semiconductor layer surrounded by dielectric materials from the semiconductor layer; a third process for producing a film of Si.sub.3 N.sub.4 on the island of semiconductor layer, or on a film of SiO.sub.2 formed on the island; a fourth process for removing the film of Si.sub.3 N.sub.4 at a predetermined region on the island; and a fifth process for irradiating with scanning an energy beam to the island of semiconductor layer so as to melt and recrystallize the island, thereby monocrystallizing or increasing the size of crystal grains at at least a partial region thereof.
    Type: Grant
    Filed: December 3, 1984
    Date of Patent: April 28, 1987
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigeru Kusunoki, Tadashi Nishimura, Kazuyuki Sugahara
  • Patent number: 4523962
    Abstract: A method for fabricating a monocrystalline semiconductor layer on an insulating layer in the production of a semiconductor device wherein the location of grain boundaries is accurately controlled, thereby making the crystal orientation of the monocrystalline semiconductor layer uniform over a large area. An antireflection layer is formed above a polycrystalline of amorphous semiconductor layer formed on a main face of a monocrystalline semiconductor substrate which contacts the monocrystalline semiconductor substrate through windows formed in a thick insulating layer. The antireflection layer includes a first portion which covers all of the area of the polycrystalline or amorphous semiconductor layer above the windows, and a second portion, which has the form of a grid composed of parallel lines extending from the first portion in the direction of the crystallographic axis of the monocrystalline semiconductor substrate and partially covering a second area between the first areas.
    Type: Grant
    Filed: December 13, 1983
    Date of Patent: June 18, 1985
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tadashi Nishimura
  • Patent number: 4514895
    Abstract: A method of manufacturing MOS field-effect transistors using a wafer (40) having a polycrystal or amorphous semiconductor layer formed on an insulator comprises a step in which an energy beam (44) is applied to the semiconductor layer by scanning the beam intermittently and correlatively to the wafer so as to heat locally the semiconductor layer whereby only a plurality of portions (41) contained in the semiconductor layer and assigned for forming channel regions of MOS field-effect transistors are monocrystallized or the crystalline grains in the above described positions are made large. According to the present invention, a strain occurring in a recrystallized semiconductor can be mitigated by the selective heating.
    Type: Grant
    Filed: March 6, 1984
    Date of Patent: May 7, 1985
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tadashi Nishimura
  • Patent number: 4465529
    Abstract: A method for producing an impurity containing semiconductor substrate includes depositing an impurity on selected portions of the substrate by placing a charge on the substrate and converting a gaseous impurity containing atmosphere into a plasma. The impurity may then be diffused into the substrate to a controlled and shallow depth by employing a laser or the like to selectively irradiate the impurity.
    Type: Grant
    Filed: June 4, 1982
    Date of Patent: August 14, 1984
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideaki Arima, Tadashi Nishimura, Masahiro Yoneda, Takaaki Fukumoto, Yoshihiro Hirata
  • Patent number: 4425062
    Abstract: A cutting and chamfering apparatus for opposite ends of a tubular member including a cutting and chamfering support for holding horizontally the member, two tables provided respectively at opposite ends of the support, and a cutting machine and chamfering machine mounted in combination on each of the tables.
    Type: Grant
    Filed: September 14, 1981
    Date of Patent: January 10, 1984
    Assignee: Kabushiki Kaisha Kobe Seiko Sho
    Inventors: Teruaki Kawamura, Tadashi Nishimura, Kazuo Akagi, Ryujiro Shitamatsu
  • Patent number: 4414242
    Abstract: A process for producing a semiconductor device includes the step of locally heating and fusing an island of a polycrystalline or amorphous semiconductor layer which is formed on and surrounded by an insulator. In the process, at least one ridge is formed on the underlying insulator before the formation of the semiconductor layer.
    Type: Grant
    Filed: November 24, 1982
    Date of Patent: November 8, 1983
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tadashi Nishimura, Yoji Mashiko
  • Patent number: 4397328
    Abstract: A cleaning apparatus for use in pickling facilities for tubular members such as zirconium or zirconium alloy tubes. The apparatus includes a travelling crane for conveying and loading the tubular members from one cleaning tank to another, a pair of endless wrapping connectors such as endless chains spacedly and circulatably provided in at least one tank, for example, in a first cleaning tank filled with slightly warm water below the level of its cleaning fluid, and a plurality of feed claws provided with an interval therebetween on each of the endless wrapping connectors along the length of the same so as to prevent the tubular members from contacting one another during cleaning treatment. Thus, development of stain or physical damage such as scratches or dents is eliminated or minimized. It is possible to tentatively stock the tubular members on the endless wrapping connectors so as to perform a smooth and continuous pickling and cleaning operation of such tubular members.
    Type: Grant
    Filed: October 5, 1981
    Date of Patent: August 9, 1983
    Assignee: Kabushiki Kaisha Kobe Seiko Sho
    Inventors: Yoshiro Tanaka, Hayato Moroi, Yukihiko Kamatsu, Kazuo Akagi, Ryujiro Shitamatsu, Tadashi Nishimura
  • Patent number: 4392267
    Abstract: An apparatus for continuously pickling the outer surfaces of hermetically plugged tubular members is described. The apparatus includes a plurality of liquid tanks which separately contain different pickling liquids and define through-holes in their respective front and rear walls on at least one common longitudinal line to permit the successive passage of the tubular members therethrough while rotating them around their respective longitudinal axes. The apparatus includes a cleaning tank and cleaning brush unit provided sequentially before the liquid tanks. The cleaning tank includes at least one ultrasonic cleaning oscillator and defines through-holes in the front and rear walls thereof for allowing said tubular members to pass through the cleaning tank and the brush unit. Since any oil, grease or dust can be completely removed by the cleaning tank and brush unit prior to pickling, it is possible to obtain tubular members having excellent outer surface quality.
    Type: Grant
    Filed: October 1, 1981
    Date of Patent: July 12, 1983
    Assignee: Kabushiki Kaisha Kobe Seiko Sho
    Inventors: Yoshiro Tanaka, Hayato Moroi, Yukihiko Komatsu, Kazuo Akagi, Ryujiro Shitamatsu, Tadashi Nishimura
  • Patent number: 4392506
    Abstract: An apparatus for conveying tubular members along a plurality of treatment liquid tanks in pickling facilities. The apparatus includes a pair of guide rails and a travelling car adapted to reciprocate on the guide rails. The travelling car includes at least one pair of tube-supporting hooks which can be reciprocated upwardly and downwardly and turned between positions parallel to the rails and other positions perpendicular to the rails. The tube-supporting hooks can be lowered or raised independently so as to support the tubular members aslant near the treatment liquid level in each of the treatment liquid tanks, thereby allowing immersion of the tubular members into the treatment liquid or retraction of the tubular members out of the treatment liquid without forming considerable air bubbles in the liquid. Since such bubbles are known to develop stains on the tubular members, tubular members of high surface quality can be obtained.
    Type: Grant
    Filed: October 1, 1981
    Date of Patent: July 12, 1983
    Assignee: Kabushiki Kaisha Kobe Seiko Sho
    Inventors: Yoshiro Tanaka, Hayato Moroi, Yukihiko Komatsu, Kazuo Akagi, Ryujiro Shitamatsu, Tadashi Nishimura
  • Patent number: 4367263
    Abstract: A magnetic recording medium comprises a first magnetic layer containing magnetite or a cobalt doped magnetite which is coated on a non-magnetic substrate; and a second magnetic layer coating a cobalt doped .gamma.-Fe.sub.2 O.sub.3 which is coated on said first magnetic layer.The magnetic recording medium has a high recording sensitivity, a high dynamic range, a less output fluctuation and especially superior sensitivity in low frequency band and superior maximum output level without a deterioration of transfer characteristics.
    Type: Grant
    Filed: June 17, 1981
    Date of Patent: January 4, 1983
    Assignee: TDK Electronics Co., Ltd.
    Inventors: Hiroshi Kawahara, Tadashi Nishimura, Masatsugu Funakoshi, Masaharu Nishimatsu