Patents by Inventor Tadashi Nishimura
Tadashi Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6319805Abstract: A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.Type: GrantFiled: February 8, 2000Date of Patent: November 20, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshiaki Iwamatsu, Yasuo Inoue, Yasuo Yamaguchi, Tadashi Nishimura
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Patent number: 6214664Abstract: In a semiconductor device and a method of manufacturing the same, an isolating and insulating film is provided at an end neighboring to a second impurity region with a groove extended to a semiconductor substrate. This removes a crystal defect existed at the end of the isolating and insulating film, and thus prevents leak of a current at this portion from a storage node. Consequently, provision of the groove at the edge portion of the isolating oxide film neighboring to the impurity region removes a crystal defect at this region, and thus eliminates a possibility of leak of a current.Type: GrantFiled: November 18, 1999Date of Patent: April 10, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiroshi Kimura, Tadashi Nishimura, Takahiro Tsuruda, Kazutami Arimoto, Tadato Yamagata, Kazuyasu Fujishima
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Patent number: 6198134Abstract: According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.Type: GrantFiled: April 8, 1998Date of Patent: March 6, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasuo Inoue, Tadashi Nishimura, Yasuo Yamaguchi, Toshiaki Iwamatsu
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Patent number: 6069379Abstract: In a semiconductor device and a method of manufacturing the same, an isolating and insulating film is provided at an end neighboring to a second impurity region with a groove extended to a semiconductor substrate. This removes a crystal defect existed at the end of the isolating and insulating film, and thus prevents leak of a current at this portion from a storage node. Consequently, provision of the groove at the edge portion of the isolating oxide film neighboring to the impurity region removes a crystal defect at this region, and thus eliminates a possibility of leak of a current.Type: GrantFiled: November 6, 1997Date of Patent: May 30, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiroshi Kimura, Tadashi Nishimura, Takahiro Tsuruda, Kazutami Arimoto, Tadato Yamagata, Kazuyasu Fujishima
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Patent number: 6051494Abstract: A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.Type: GrantFiled: May 13, 1997Date of Patent: April 18, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshiaki Iwamatsu, Yasuo Inoue, Yasuo Yamaguchi, Tadashi Nishimura
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Patent number: 5986037Abstract: There is provided a polycarbonate resin with a reduced volatile chlorine content in which the amount of a chlorinous matter as volatilized from the resin when the resin is heated at 280.degree. C. for 30 minutes and then allowed to stand at room temperature for 3 days is 30 ppb or lower as calculated in terms of the amount of Cl atom. There is also provided a process for producing a polycarbonate resin using phosgene as a raw material, the improvement comprising using phosgene having a chlorine concentration of up to 1,000 ppb as the raw material thereby to provide the resin with a reduced volatile chlorine content.Type: GrantFiled: December 9, 1997Date of Patent: November 16, 1999Assignee: Mitsubishi Chemical CorporationInventors: Masaaki Miyamoto, Kenji Tsuruhara, Tadashi Nishimura
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Patent number: 5937284Abstract: Generation of parasitic transistor in active layer edge is prevented. In an NMOS region of a semiconductor layer (21) on an insulating film (20), boron ions are implanted by rotary oblique injection, using a nitride film (23) and a resist (253a) as mask. In the vicinity of a region for separating element by LOCOS method, that is, only in the edge region of the semiconductor layer (21) as the active layer of NMOS transistor, boron ions are implanted by about 3.times.10.sup.13 /cm.sup.2. After LOCOS oxidation, the impurity concentration is heightened to such a level as the boron ions may not be sucked up into the oxide film.Type: GrantFiled: November 28, 1997Date of Patent: August 10, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshiaki Iwamatsu, Yasuo Inoue, Tadashi Nishimura
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Patent number: 5891265Abstract: Oxygen ion is implanted into a silicon substrate to remain a silicon layer on a surface of the silicon substrate. In this state, a silicon oxide layer is formed under the silicon layer. Silicon oxide particles are formed and remained in the residual silicon layer. While maintaining this state, the silicon substrate is heated to a predetermined temperature not less than 1300.degree. C. Alternatively, the silicon substrate is heated at a high temperature-rise rate to 900-1100.degree. C., and thereafter is heated at a low temperature-rise rate to the temperature not less than 1300.degree. C. The silicon substrate is held at the predetermined temperature not less than 1300.degree. C. for a predetermined time, whereby crystallinity of the residual silicon layer is restored.Type: GrantFiled: August 6, 1997Date of Patent: April 6, 1999Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Material CorporationInventors: Tetsuya Nakai, Hiroshi Shinyashiki, Yasuo Yamaguchi, Tadashi Nishimura
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Patent number: 5801080Abstract: According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.Type: GrantFiled: April 14, 1997Date of Patent: September 1, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasuo Inoue, Tadashi Nishimura, Yasuo Yamaguchi, Toshiaki Iwamatsu
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Patent number: 5741717Abstract: Oxygen ion is implanted into a silicon substrate to remain a silicon layer on a surface of the silicon substrate. In this state, a silicon oxide layer is formed under the silicon layer. Silicon oxide particles are formed and remained in the residual silicon layer. While maintaining this state, the silicon substrate is heated to a predetermined temperature not less than 1300.degree. C. Alternatively, the silicon substrate is heated at a high temperature-rise rate to 900.degree.-1100.degree. C., and thereafter is heated at a low temperature-rise rate to the temperature not less than 1300.degree. C. The silicon substrate is held at the predetermined temperature not less than 1300.degree. C. for a predetermined time, whereby crystallinity of the residual silicon layer is restored.Type: GrantFiled: February 21, 1995Date of Patent: April 21, 1998Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Material CorporationInventors: Tetsuya Nakai, Hiroshi Shinyashiki, Yasuo Yamaguchi, Tadashi Nishimura
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Patent number: 5721444Abstract: A buried insulating layer is provided in a semiconductor substrate, in a position separated from its major surface. A LOCOS isolation film is provided in the major surface of the semiconductor substrate for isolating an active region from other active regions. A thin-film transistor is provided in the active region. The thin-film transistor comprises a gate electrode which is provided on the active region with interposition of a gate insulating layer. A pair of source/drain layers are provided in the major surface of the semiconductor substrate on both sides of the gate electrode. A high-concentration impurity layer is provided in the semiconductor substrate immediately under the buried insulating layer.Type: GrantFiled: March 25, 1997Date of Patent: February 24, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshiyuki Oashi, Jiro Matsufusa, Takahisa Eimori, Tadashi Nishimura
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Patent number: 5659194Abstract: A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.Type: GrantFiled: March 12, 1996Date of Patent: August 19, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshiaki Iwamatsu, Yasuo Inoue, Yasuo Yamaguchi, Tadashi Nishimura
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Patent number: 5652454Abstract: According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.Type: GrantFiled: July 3, 1996Date of Patent: July 29, 1997Inventors: Toshiaki Iwamatsu, Yasuo Inoue, Yasuo Yamaguchi, Tadashi Nishimura
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Patent number: 5619053Abstract: Generation of parasitic transistor in active layer edge is prevented, in an NMOS region of a semiconductor layer (21) on an insulating film (20), boron ions are implanted by rotary oblique injection, using a nitride film (23) and a resist (253a) as mask. In the vicinity of a region for separating element by LOCOS method, that is, only in the edge region of the semiconductor layer (21) as the active layer of NMOS transistor, boron ions are implanted by about 3.times.10.sup.13 /cm.sup.2. After LOCOS oxidation, the impurity concentration is heightened to such a level as the boron ions may not be sucked up into the oxide film.Type: GrantFiled: May 31, 1995Date of Patent: April 8, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshiaki Iwamatsu, Yasuo Inoue, Tadashi Nishimura
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Patent number: 5616507Abstract: A polysilicon layer is formed on a surface of a silicon substrate after oxygen ions are implanted into the silicon substrate and an SiO.sub.2 film is formed in the silicon substrate at a position in a prescribed depth from the surface of silicon substrate. A heat treatment is performed to a silicon layer between the polysilicon layer and the SiO.sub.2 film, thereby providing an SOI layer with improved crystal quality.Type: GrantFiled: May 19, 1995Date of Patent: April 1, 1997Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Materials CorporationInventors: Tetsuya Nakai, Yasuo Yamaguchi, Tadashi Nishimura
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Patent number: 5557231Abstract: A semiconductor device including an NMOS transistor includes a first bias generating circuit 30 for generating a substrate bias VBB1 for making smaller the amount of leak current in an inactive state, a second bias generating circuit 31 for generating a substrate bias VBB2 for increasing drivability of supplying current in the active state of the NMOS transistor, and a bias selecting circuit 32 responsive to a control signal CNT for supplying the substrate bias VBB2 instead of the substrate bias VBB1 to the silicon substrate 1. By changing the potential of the substrate bias in the standby state and the active state, power consumption in the standby state can be reduced and the speed of operation in the active state can be improved.Type: GrantFiled: August 15, 1994Date of Patent: September 17, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasuo Yamaguchi, Tadashi Nishimura
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Patent number: 5471086Abstract: Disclosed herein a semiconductor pressure sensor, which is capable of carrying out temperature compensation in high accuracy, having a piezo resistance layer consisting of a single crystal layer formed by lateral seeding. In this semiconductor pressure sensor, a piezo resistance is so formed as to contain no crystal sub-grain boundary. Thus prevented is inconvenience of reduction in resistance temperature coefficient, which is caused when the piezo resistance contains the crystal sub-grain boundary. Thus, the piezo resistance can be set at a high resistance temperature coefficient, whereby a semiconductor pressure sensor capable of carrying out temperature compensation in high accuracy is obtained.Type: GrantFiled: October 31, 1992Date of Patent: November 28, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takashi Ipposhi, Tadashi Nishimura
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Patent number: 5441899Abstract: A polysilicon or amorphous Si layer is formed on a surface of a silicon substrate. Oxygen ions are implanted into the silicon substrate through the polysilicon layer, and an SiO.sub.2 film is formed in the silicon substrate at a position in a prescribed depth from the surface of silicon substrate. A heat treatment is performed to a silicon layer between the polysilicon layer and the SiO.sub.2 film, thereby providing an SOI layer with improved crystal quality.Type: GrantFiled: February 12, 1993Date of Patent: August 15, 1995Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Materials CorporationInventors: Tetsuya Nakai, Yasuo Yamaguchi, Tadashi Nishimura
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Patent number: 5440161Abstract: A buried oxide film 4 is formed on a main surface of a silicon substrate 1. An SOI layer 5 is formed on buried oxide film 4. Channel stop regions 22a and 22b respectively connected to channel regions of an nMOS 2 and a pMOS 3 are formed in an element isolation region of SOI layer 5. nMOS 2 and pMOS 3 are formed in an element formation region of SOI layer. A concentration of a p type impurity or an n type impurity included in channel stop regions 22a and 22b is higher than a concentration of the p type impurity or the n type impurity included in the channel region of nMOS 2 or the channel region of pMOS 3. An FS gate 16 is formed on channel stop regions 22a and 22b with an FS gate oxide film 15 interposed therebetween. Therefore, a semiconductor device having an SOI structure which is capable of suppressing a parasitic bipolar operation by drawing out efficiently excessive carriers stored in the channel region of transistor can be obtained.Type: GrantFiled: July 26, 1994Date of Patent: August 8, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshiaki Iwamatsu, Yasuo Yamaguchi, Yasuo Inoue, Tadashi Nishimura
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Patent number: 5424225Abstract: An MOS field effect transistor comprises a channel region (6) of a first conductivity type formed in a semiconductor layer (3) on an insulator substrate (2), a source region (8) and a drain region (9) of a second conductivity type formed in contact with one and the other sides of the channel region (6) in the semiconductor layer (3), respectively, a body region (7) formed in contact with at least a part of the channel region (6) and a part of a periphery of the source region (8) in the semiconductor layer (3) and having a higher impurity concentration than that of the channel region (6), a gate dielectric thin film (4) and a gate electrode (5) formed on the channel region (6), and a conductor (14a) connected in common to the source region (8) and the body region (7).Type: GrantFiled: June 30, 1994Date of Patent: June 13, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasuo Yamaguchi, Tadashi Nishimura