Patents by Inventor Tadashi Takeuchi

Tadashi Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180217875
    Abstract: A data processing system in which application nodes capable of executing a program are provided at sites at a plurality of locations, and storage nodes for storing data are also provided at the plurality of locations, with these locations being coupled to one another via a network, wherein: a first application node stores a program I/O history; a second application node reproduces I/O events on the basis of the I/O history, thereby estimating data processing performance; and the first application node determines, on the basis of the data processing performance estimation, whether or not to transfer the program to the second application node.
    Type: Application
    Filed: February 17, 2016
    Publication date: August 2, 2018
    Inventors: Tadashi TAKEUCHI, Hideo AOKI, Tsuyoshi TANAKA, Yuuya ISODA
  • Patent number: 10013358
    Abstract: A computer system includes: a physical resource including a memory; a virtualization mechanism that provides a virtual computer to which the physical resource is allocated; and a cache state management mechanism that manages a cache state of the virtual computer. The virtualization mechanism provides a first virtual computer and a second virtual computer. The cache state management mechanism manages the cache state of each of the first virtual computer and the second virtual computer. When the cache state management mechanism detects transition of the cache state in a state where a memory area allocated to a cache of the first virtual computer and a memory area allocated to a cache of the second virtual computer include duplicated areas storing same data, the virtualization mechanism releases the duplicated area in one of the first virtual computer and the second virtual computer.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: July 3, 2018
    Assignee: HITACHI, LTD.
    Inventors: Sachie Tajima, Tadashi Takeuchi
  • Publication number: 20180004447
    Abstract: The storage system is capable of creating one or more virtual storage subsystems to which virtual resources having logically divided a processing capacity of the physical resources are allocated, and upon creating a virtual volume for receiving I/O requests from the host within the virtual storage subsystem, the virtual storage subsystem allocates the virtual resource to the virtual volume, and when an I/O request to the virtual volume is received from the host, performs processing related to the I/O request using the virtual resource having been allocated. According further to the storage system, after allocating the virtual resource to the virtual volume, the storage system raises a utilization rate of the virtual resource allocated to the virtual volume in a stepwise manner.
    Type: Application
    Filed: January 29, 2015
    Publication date: January 4, 2018
    Inventors: Yoshinori OOHIRA, Nobuhiro MAKI, Wataru OKADA, Tadashi TAKEUCHI, Sachie TAJIMA
  • Patent number: 9632931
    Abstract: In a computer system in which a virtualization control unit controls a plurality of virtual machines, if memory is collected regardless of a memory usage status of the virtual machine, cache miss increases and an IO performance of overall system deteriorates. In order to solve this problem, a usage status of a cache region within a memory which is utilized by each OS that the plurality of the virtual machines has, and based on a monitoring result, the virtualization control unit decides an allocation region of the memory as a collection target among the allocation region of the memory already allocated to each OS, and collects the allocation region of the memory as the collection target from the OS as a current allocation destination.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: April 25, 2017
    Assignee: Hitachi, Ltd.
    Inventors: Sachie Tajima, Tadashi Takeuchi
  • Publication number: 20170075816
    Abstract: A control apparatus, in a storage system, accesses a specific storage area in a shared memory by designating a fixed virtual address, even when a capacity of the shared memory in the storage system changes. A space of a physical address indicating a storage area in a plurality of memories in a self-control-subsystem of two control-subsystems and a space of a physical address indicating a storage area in the plurality of memories in the other-control-subsystem are associated with a space of a virtual address used by each of a processor and an input/output device in the self-control-subsystem. Upon receiving data transferred from the other-control-subsystem to the self-control-subsystem, a relay device translates a virtual address indicating a transfer destination of the data designated by the other-control-subsystem into a virtual address in the self-control-subsystem based on an offset determined in advance, and transfers the data to the translated virtual address.
    Type: Application
    Filed: April 24, 2014
    Publication date: March 16, 2017
    Applicant: HITACHI, LTD.
    Inventors: Naoya OKADA, Masanori TAKADA, Shintaro KUDO, Yusuke NONAKA, Tadashi TAKEUCHI
  • Publication number: 20160378533
    Abstract: A simple hypervisor, in addition to a hypervisor, is operated on a computer. A guest OS, the continued operations of which need to be guaranteed, when a fault occurs in the hypervisor is operated on the simple hypervisor, and the other guest OSs are operated on the hypervisor. The hypervisor performs resource scheduling (determining of resources to be allocated to or deallocated from each guest OS) and the simple hypervisor executes, in place of the simple hypervisor, allocation or deallocation of resources to or from the guest OS, the continued operations of which need to be guaranteed.
    Type: Application
    Filed: February 17, 2014
    Publication date: December 29, 2016
    Inventors: Tadashi TAKEUCHI, Sachie TAJIMA
  • Publication number: 20160335192
    Abstract: A computer system includes: a physical resource including a memory; a virtualization mechanism that provides a virtual computer to which the physical resource is allocated; and a cache state management mechanism that manages a cache state of the virtual computer. The virtualization mechanism provides a first virtual computer and a second virtual computer. The cache state management mechanism manages the cache state of each of the first virtual computer and the second virtual computer. When the cache state management mechanism detects transition of the cache state in a state where a memory area allocated to a cache of the first virtual computer and a memory area allocated to a cache of the second virtual computer include duplicated areas storing same data, the virtualization mechanism releases the duplicated area in one of the first virtual computer and the second virtual computer.
    Type: Application
    Filed: July 24, 2014
    Publication date: November 17, 2016
    Applicant: HITACHI, LTD.
    Inventors: Sachie TAJIMA, Tadashi TAKEUCHI
  • Patent number: 9430266
    Abstract: A control method for an I/O device, the I/O device being shared by a hypervisor and a first guest OS, the hypervisor comprising a physical driver for using a physical function, the first guest OS comprising a virtual driver for using a virtual function, the control method comprising: a first step of acquiring, by the hypervisor, a state of the I/O device via the physical driver; a second step of monitoring, by the first guest OS, the hypervisor, thereby determining whether the hypervisor has been brought into a predetermined state or not; a third step of activating, by the first guest OS, a sub physical driver for operating the I/O device when the first guest OS determines that the hypervisor has been brought into the predetermined state; and a fourth step of carrying out, by the first guest OS, transmission/reception via a queue set in advance on the memory.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: August 30, 2016
    Assignee: Hitachi, Ltd.
    Inventor: Tadashi Takeuchi
  • Publication number: 20160214226
    Abstract: A machining system with a configuration in which working machines, including a machine tool, are configured to be disposed in a line, and in which multiple working machines perform operations on one work in order, is provided. The machining system includes: a base; and multiple working machine modules which are mounted on the base and are arranged in an arrangement direction, and has a configuration in which each of the multiple working machine modules is capable of being drawn out from the base along a track extending in an intersecting direction intersecting with the arrangement direction.
    Type: Application
    Filed: September 13, 2013
    Publication date: July 28, 2016
    Applicant: FUJI MACHINE MFG. CO., LTD.
    Inventors: Kazuyoshi NAGATO, Shigefumi SUZUYAMA, Kenji MIZUTA, Toshifumi SUZUKI, Tadashi TAKEUCHI, Kazutoshi SAKAI, Kazuya FURUKAWA, Atsushi KAMIYA, Shinya KUMAZAKI, Jun YANAGISAKI, Osamu NAGAI
  • Publication number: 20160214227
    Abstract: A machining system with a configuration in which working machines, including a machine tool, are configured to be disposed in a line, and in which multiple working machines perform operations on one work in order, is provided. The machining system includes: a base; and multiple working machine modules which are mounted on the base and are arranged in an arrangement direction, and has a configuration in which each of the multiple working machine modules is capable of being drawn out from the base along a track extending in an intersecting direction intersecting with the arrangement direction.
    Type: Application
    Filed: September 13, 2013
    Publication date: July 28, 2016
    Applicant: FUJI MACHINE MFG. CO., LTD.
    Inventors: Kazuyoshi NAGATO, Shigefumi SUZUYAMA, Kenji MIZUTA, Toshifumi SUZUKI, Tadashi TAKEUCHI, Kazutoshi SAKAI, Kazuya FURUKAWA, Atsushi KAMIYA, Shinya KUMAZAKI, Jun YANAGISAKI, Osamu NAGAI
  • Publication number: 20150378892
    Abstract: In a computer system in which a virtualization control unit controls a plurality of virtual machines, if memory is collected regardless of a memory usage status of the virtual machine, cache miss increases and an IO performance of overall system deteriorates. In order to solve this problem, a usage status of a cache region within a memory which is utilized by each OS that the plurality of the virtual machines has, and based on a monitoring result, the virtualization control unit decides an allocation region of the memory as a collection target among the allocation region of the memory already allocated to each OS, and collects the allocation region of the memory as the collection target from the OS as a current allocation destination.
    Type: Application
    Filed: September 26, 2013
    Publication date: December 31, 2015
    Applicant: Hitachi, Ltd.
    Inventors: Sachie TAJIMA, Tadashi TAKEUCHI
  • Publication number: 20140149985
    Abstract: A control method for an I/O device, the I/O device being shared by a hypervisor and a first guest OS, the hypervisor comprising a physical driver for using a physical function, the first guest OS comprising a virtual driver for using a virtual function, the control method comprising: a first step of acquiring, by the hypervisor, a state of the I/O device via the physical driver; a second step of monitoring, by the first guest OS, the hypervisor, thereby determining whether the hypervisor has been brought into a predetermined state or not; a third step of activating, by the first guest OS, a sub physical driver for operating the I/O device when the first guest OS determines that the hypervisor has been brought into the predetermined state; and a fourth step of carrying out, by the first guest OS, transmission/reception via a queue set in advance on the memory.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 29, 2014
    Applicant: HITACHI, LTD.
    Inventor: Tadashi TAKEUCHI
  • Patent number: 8504780
    Abstract: A computer includes first and second processors, first and second I/O devices, a shared memory, and an interrupt controller. The first processor issues a control command for causing the first I/O device to read target data from the first apparatus and store the target data in the shared memory. The first I/O device reads the target data from the first apparatus and, transfers the target data to the shared memory, and generates an I/O complete interrupt. The interrupt controller delivers the generated I/O complete interrupt to the second processor. When the second processor receives the I/O complete interrupt, the second processor issues a control command for causing the second I/O device to read the target data from the shared memory and send the target data to the second apparatus. The second I/O device reads the target data from the shared memory and sends the target data to the second apparatus.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: August 6, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Mine, Ken Nomura, Damien Le Moal, Tadashi Takeuchi
  • Patent number: 8499112
    Abstract: An aspect of the invention is a storage control apparatus, comprising a plurality of processors, a memory, an I/O device coupled to a storage device, a virtualization module that allocates a first processor to a first guest and a second processor to a second guest from among the plurality of processors, and an interrupt control module that receives an interrupt from the I/O device and transmits the interrupt to any one of the plurality of processors, wherein the virtualization module comprises, a state detection module that detects at least one of a state of the first guest and a state of the first processor, and an interrupt delivery destination control module that switches the interrupt with respect to the first processor to the second processor when at least one of the state of the first guest and the state of the first processor becomes a predetermined state.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: July 30, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Mine, Ken Nomura, Damien Le Moal, Tadashi Takeuchi, Masaaki Iwasaki
  • Publication number: 20130046911
    Abstract: An aspect of the invention is a storage control apparatus, comprising a plurality of processors, a memory, an I/O device coupled to a storage device, a virtualization module that allocates a first processor to a first guest and a second processor to a second guest from among the plurality of processors, and an interrupt control module that receives an interrupt from the I/O device and transmits the interrupt to any one of the plurality of processors, wherein the virtualization module comprises, a state detection module that detects at least one of a state of the first guest and a state of the first processor, and an interrupt delivery destination control module that switches the interrupt with respect to the first processor to the second processor when at least one of the state of the first guest and the state of the first processor becomes a predetermined state.
    Type: Application
    Filed: August 16, 2011
    Publication date: February 21, 2013
    Applicant: HITACHI, LTD.
    Inventors: Hiroshi Mine, Ken Nomura, Damien Le Moal, Tadashi Takeuchi, Masaaki Iwasaki
  • Publication number: 20120260017
    Abstract: A computer includes first and second processors, first and second I/O devices, a shared memory, and an interrupt controller. The first processor issues a control command for causing the first I/O device to read target data from the first apparatus and store the target data in the shared memory. The first I/O device reads the target data from the first apparatus and, transfers the target data to the shared memory, and generates an I/O complete interrupt. The interrupt controller delivers the generated I/O complete interrupt to the second processor. When the second processor receives the I/O complete interrupt, the second processor issues a control command for causing the second I/O device to read the target data from the shared memory and send the target data to the second apparatus. The second I/O device reads the target data from the shared memory and sends the target data to the second apparatus.
    Type: Application
    Filed: April 8, 2011
    Publication date: October 11, 2012
    Applicant: HITACHI, LTD.
    Inventors: Hiroshi Mine, Ken Nomura, Damien Le Moal, Tadashi Takeuchi
  • Patent number: 8260947
    Abstract: A media delivery apparatus for relaying media data streaming-delivered from a server to a client terminal through a network, including a receiving portion for receiving packets transmitted from the server to the network when stream-delivering the media data, and a storage device, wherein: each of the packets contains at least one media data element as a split of the media data and is constructed according to a certain protocol; and the receiving portion extracts the media data element, generates information necessary for reconstructing a packet having the same construction as that of the packet containing the media data and stores the necessary information in addition to the extracted media data in the storage device.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: September 4, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Mine, Tadashi Takeuchi, Ken Nomura
  • Patent number: 8250180
    Abstract: A content delivery system includes a delivery server, a storage apparatus having a logical unit for storing data regarding content items, and a management apparatus having a content management unit for managing a delivery server. The delivery server includes a conversion unit and a delivery unit. The conversion units acquires original data regarding a content item from an external origin server in response to a content addition request from the content management unit, converts the original data to data for delivery, and stores the content data for delivery in the first logical unit. The delivery unit reads, in response to a content delivery request from the client, the data for delivery from the logical unit and transmits it to the client.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: August 21, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihiro Hayashi, Tadashi Takeuchi
  • Patent number: 8250110
    Abstract: A proxy server 10 transfers, when a protocol header and content specified in a distribution request from a client 18 are not stored in a storage device 28, the distribution request to an origin server 12; stores the protocol header and content, which have been transmitted from the origin server 12, in the storage device 28; transmits the protocol header and content to the client 18; creates another protocol header based on the protocol header transmitted from the origin server 12; and stores the created protocol header in the storage device 28. When the protocol header and content specified in the distribution request from the client 18 have been stored in the storage device 28, the proxy server 10 extracts the protocol header and content from the storage device 28 and distributes them to the client 18.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: August 21, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Koji Watanabe, Tadashi Takeuchi, Daisuke Yokota
  • Patent number: 8234447
    Abstract: A plurality of storage devices are coupled with at least two switch of a switch network that is configured by a plurality of switches that transfer a packet that complies with an IP (Internet Protocol). Moreover, a storage control device is coupled with the switch network. The storage control device builds an LU (Logical Unit) that is utilized by a host device based on at least two storage devices that are coupled with different switches.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: July 31, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Aritoki Takada, Ken Nomura, Tadashi Takeuchi, Damien Le Moal, Hiroshi Mine