Patents by Inventor Tadatomo Suga

Tadatomo Suga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060192578
    Abstract: Disclosed is an inspection method for inspecting the electrical characteristics of a device by bringing an inspecting probe into electrical contact with an inspection electrode. An insulating film formed on the surface of the inspection electrode is broken by utilizing a fritting phenomenon so as to bring the inspection electrode into electrical contact with the inspection electrode.
    Type: Application
    Filed: May 2, 2006
    Publication date: August 31, 2006
    Applicants: TOKYO ELECTON LIMITED, TADATOMO SUGA, TOSHIHIRO ITOH
    Inventors: Shinji Iino, Kiyoshi Takekoshi, Tadatomo Suga, Toshihiro Itoh, Kenichi Kataoka
  • Patent number: 7078811
    Abstract: There are provided a semiconductor device and method for fabricating the device capable of achieving reliable electrical connection by securely directly bonding conductors to each other even though bonding surfaces are polished by a CMP method and solid-state-bonded to each other. By polishing according to the CMP method, a through hole conductor 5 and a grounding wiring layer 10, which are made of copper, become concave in a dish-like shape and lowered in level, causing a dishing portion 17 since they have a hardness lower than that of a through hole insulator 11 made of silicon nitride. The through hole insulator 11 is selectively etched by a reactive ion etching method until the through hole insulator 11 comes to have a height equal to the height of a bottom portion 19 of the dishing portion 17 of the through hole conductor 5. The through hole conductors 5 and 25 are aligned with each other, and the bonding surfaces 12 and 22 are bonded to each other in a solid state bonding manner.
    Type: Grant
    Filed: July 5, 2001
    Date of Patent: July 18, 2006
    Assignees: Sharp Kabushiki Kaisha
    Inventor: Tadatomo Suga
  • Publication number: 20060145716
    Abstract: At least one pair of electrode formed on a mounting surface of a stage is in contact with a conductive layer formed on a first surface of an inspection object, and an electrical path is formed between the both by using a fritting phenomenon.
    Type: Application
    Filed: December 8, 2005
    Publication date: July 6, 2006
    Inventors: Shigekazu Komatsu, Tadatomo Suga, Toshihiro Itoh, Kenichi Kataoka
  • Patent number: 7061259
    Abstract: Disclosed is an inspection method for inspecting the electrical characteristics of a device by bringing an inspecting probe into electrical contact with an inspection electrode. An insulating film formed on the surface of the inspection electrode is broken by utilizing a fritting phenomenon so as to bring the inspection electrode into electrical contact with the inspection electrode.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: June 13, 2006
    Assignees: Tokyo Electron Limited
    Inventors: Shinji Iino, Kiyoshi Takekoshi, Tadatomo Suga, Toshihiro Itoh, Kenichi Kataoka
  • Publication number: 20060085965
    Abstract: A device and method for bonding objects to be bonded each having a metal bonding portion on a substrate, comprising cleaning means for exposing the metal bonding portions to a plasma having an energy enough to etch the surfaces of the metal bonding portions at a depth of 1.6 nm or more over the entire surfaces of the metal bonding portions under a reduced pressure and bonding means for bonding the metal bonding portions of the objects taken out of the cleaning means in an atmospheric air. By using a specific scheme, metal bonding portions after the plasma cleaning can be bonded in the atmospheric air, thereby significantly simplifying the bonding process and the whole device and lowering the cost.
    Type: Application
    Filed: September 22, 2003
    Publication date: April 27, 2006
    Inventors: Tadatomo Suga, Toshihiro Ito, Akira Yamauchi
  • Publication number: 20060043552
    Abstract: The present invention relates to a semiconductor device in which electrodes formed on a semiconductor chip and electrodes formed on a wiring board are electrically connected via projecting elastic electrodes, and further relates to a mounting method of reducing a pressure applied to electrodes formed on a substrate or underlying wirings when a semiconductor chip and a wiring board are bonded.
    Type: Application
    Filed: August 30, 2005
    Publication date: March 2, 2006
    Inventors: Tadatomo Suga, Toshihiro Itoh
  • Publication number: 20060043604
    Abstract: The present invention relates to a high-reliable semiconductor device in which electrodes formed on substrates are prevented from deteriorating by sealing the electrodes with a frame member rather than a sealing material. The frame member in the present invention surrounds electrodes formed on the substrates. The inside of the frame member is vacuous or filled with a gas which does not react with the electrodes such as an inert gas and, thereby, the electrodes are prevented from deteriorating by attacks of oxygen or moisture.
    Type: Application
    Filed: August 29, 2005
    Publication date: March 2, 2006
    Inventors: Tadatomo Suga, Toshihiro Itoh
  • Patent number: 6975489
    Abstract: A bypass capacitor having a given capacitance is arranged on the power/ground line adjacently to a driver circuit in a chip to reduce an effect of transient phenomenon at switching. The capacitance of the bypass capacitor is preset so as to be larger than a parasitic capacitance of the driver circuit to prevent the characteristic impedance of the power/ground line from being higher than the characteristic impedance of internal wiring.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: December 13, 2005
    Assignees: NEC Corporation, Oki Electric Industry Co., Ltd., Sanyo Electric Co., Ltd., SHARP Kabushiki Kaisha, Sony Corporatoin, TOSHIBA Corporation, Fujitsu Limited, Matsushita Electric Industrial Co., Ltd., Rohm Co., Ltd., Renesas Technology Corp.
    Inventors: Kanji Otsuka, Tadatomo Suga, Tamotsu Usami
  • Patent number: 6935553
    Abstract: A soldering method includes exposing a solder paste including a solder powder and a flux on a member to a free radical gas and heating the solder paste to reflow the solder paste and vaporize any active components in the solder paste. Any flux residue is free of active components, so it is not necessary to perform cleaning after soldering to remove flux residue.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: August 30, 2005
    Assignees: Senju Metal Industry Co., Ltd., Shinko Seiki Co., Ltd.
    Inventors: Tadatomo Suga, Keisuke Saito, Yoshikazu Matsuura, Tatsuya Takeuchi, Johji Kagami, Rikiya Kato, Sakie Yamagata
  • Publication number: 20050173057
    Abstract: A substrate bonding method for mutually bonding substrates, has a first radiation step for irradiating the surfaces of the individual substrates with an oxygen particle beam, a second radiation step for irradiating the surfaces of the individual substrate with a nitrogen particle beam simultaneously with or subsequently to the first radiation step, and a step for stacking the individual substrates and bringing the surfaces thereof into close contact. Particularly, the substrates which have been irradiated first with an oxygen plasma and subsequently with a nitrogen plasma are stacked and bonded.
    Type: Application
    Filed: August 27, 2004
    Publication date: August 11, 2005
    Inventors: Tadatomo Suga, Taehyun Kim, Tomoyuki Abe
  • Publication number: 20050170626
    Abstract: There are provided a semiconductor device and method for fabricating the device capable of achieving reliable electrical connection by securely directly bonding conductors to each other even though bonding surfaces are polished by a CMP method and solid-state-bonded to each other. By polishing according to the CMP method, a through hole conductor 5 and a grounding wiring layer 10, which are made of copper, become concave in a dish-like shape and lowered in level, causing a dishing portion 17 since they have a hardness lower than that of a through hole insulator 11 made of silicon nitride. The through hole insulator 11 is selectively etched by a reactive ion etching method until the through hole insulator 11 comes to have a height equal to the height of a bottom portion 19 of the dishing portion 17 of the through hole conductor 5. The through hole conductors 5 and 25 are aligned with each other, and the bonding surfaces 12 and 22 are bonded to each other in a solid state bonding manner.
    Type: Application
    Filed: March 11, 2005
    Publication date: August 4, 2005
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Tadatomo Suga
  • Patent number: 6887319
    Abstract: A residue-free solder paste which leaves little or no flux residue after reflow soldering and which have good printability, storage stability, retainability of parts, and wettability, comprises a solder powder mixed with a rosin-free pasty flux. The flux comprises at least one solid solvent and at least one highly viscous solvent in a total amount of 30-90 mass %, in addition to at least one liquid solvent, all the solvents vaporizing at a reflow soldering temperature. The flux may further contain 0.5-12% of a thixotropic agent such as a fatty acid amide and 1-15% of an activator selected from organic acids and their amine salts, the thixotropic agent and activator vaporizing in the presence of the solvents while the solvents are vaporizing.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: May 3, 2005
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Tadatomo Suga, Keisuke Saito, Rikiya Kato, Sakie Yamagata
  • Publication number: 20040211060
    Abstract: A method of mounting an electronic part on a board, in which an electronic part and a mounting board on which the electronic part is to be mounted are placed in a vacuum or inert atmosphere, and the electronic part is mounted on the board by bringing the bonding members of the electronic part and the board into contact with each other at normal temperature to thereby mount the electronic part on the board, the method comprising forming the bonding members of at least one of the electronic part and the board out of a solder material, and bringing the bonding members of the electronic part and the board into contact with each other without preprocessing the bonding surfaces of the bonding members.
    Type: Application
    Filed: April 21, 2004
    Publication date: October 28, 2004
    Applicants: Tadatomo SUGA, SHINKO ELECTRIC INDUSTRIES CO., LTD, Oki Electric Industry Co., Ltd., SANYO ELECTRIC CO., LTD., SHARP KABUSHIKI KAISHA, SONY CORPORATION, KABUSHIKI KAISHA TOSHIBA, NEC CORPORATION, HITACHI, LTD., FUJITSU LIMITED, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., MITSUBISHI DENKI KABUSHIKI KAISHA, ROHM CO., LTD.
    Inventors: Tadatomo Suga, Toshihiro Itoh, Hideto Nakazawa, Masatoshi Akagawa
  • Publication number: 20040174177
    Abstract: Disclosed is an inspection method for inspecting the electrical characteristics of a device by bringing an inspecting probe into electrical contact with an inspection electrode. An insulating film formed on the surface of the inspection electrode is broken by utilizing a fritting phenomenon so as to bring the inspection electrode into electrical contact with the inspection electrode.
    Type: Application
    Filed: March 18, 2004
    Publication date: September 9, 2004
    Applicants: TOKYO ELECTRON LIMITED, TADATOMO SUGA, TOSHIHIRO ITOH
    Inventors: Shinji Iino, Kiyoshi Takekoshi, Tadatomo Suga, Toshihiro Itoh, Kenichi Kataoka
  • Patent number: 6777967
    Abstract: Disclosed is an inspection method for inspecting the electrical characteristics of a device by bringing an inspecting probe into electrical contact with an inspection electrode. An insulating film formed on the surface of the inspection electrode is broken by utilizing a fritting phenomenon so as to bring the inspection electrode into electrical contact with the inspection electrode.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: August 17, 2004
    Assignees: Tokyo Electron Limited, Tadatomo Suga, Toshihiro Itoh
    Inventors: Shinji Iino, Kiyoshi Takekoshi, Tadatomo Suga, Toshihiro Itoh, Kenichi Kataoka
  • Publication number: 20040007610
    Abstract: A soldering method includes exposing a solder paste including a solder powder and a flux on a member to a free radical gas and heating the solder paste to reflow the solder paste and vaporize any active components in the solder paste. Any flux residue is free of active components, so it is not necessary to perform cleaning after soldering to remove flux residue.
    Type: Application
    Filed: April 15, 2003
    Publication date: January 15, 2004
    Inventors: Tadatomo Suga, Keisuke Saito, Yoshikazu Matsuura, Tatsuya Takeuchi, Johji Kagami, Rikiya Kato, Sakie Yamagata
  • Publication number: 20040000355
    Abstract: A residue-free solder paste which leaves little or no flux residue after reflow soldering and which have good printability, storage stability, retainability of parts, and wettability, comprises a solder powder mixed with a rosin-free pasty flux. The flux comprises at least one solid solvent and at least one highly viscous solvent in a total amount of 30-90 mass %, in addition to at least one liquid solvent, all the solvents vaporizing at a reflow soldering temperature. The flux may further contain 0.5-12% of a thixotropic agent such as a fatty acid amide and 1-15% of an activator selected from organic acids and their amine salts, the thixotropic agent and activator vaporizing in the presence of the solvents while the solvents are vaporizing.
    Type: Application
    Filed: April 15, 2003
    Publication date: January 1, 2004
    Inventors: Tadatomo Suga, Keisuke Saito, Rikiya Kato, Sakie Yamagata
  • Publication number: 20030184311
    Abstract: A bypass capacitor having a given capacitance is arranged on the power/ground line adjacently to a driver circuit in a chip to reduce an effect of transient phenomenon at switching. The capacitance of the bypass capacitor is preset so as to be larger than a parasitic capacitance of the driver circuit to prevent the characteristic impedance of the power/ground line from being higher than the characteristic impedance of internal wiring.
    Type: Application
    Filed: January 23, 2003
    Publication date: October 2, 2003
    Inventors: Kanji Otsuka, Tadatomo Suga, Tamotsu Usami
  • Publication number: 20030168145
    Abstract: A method and an apparatus for mounting: the method for bonding a plurality of objects to each other, comprising the steps of disposing, apart from each other, a first object, a second object and a holding means therefor, and a backup member having a reference positioning surface in this order, adjusting the parallelism of the second object or the holding means therefor relative to the reference positioning surface, adjusting the parallelism of the first object or the holding means therefor relative to the second object or the holding means therefor, bringing the first object into contact with the second object to temporarily bond both objects to each other, bringing the holding means for the second object into contact with the reference positioning surface of the backup member, and pressing both objects against each other for final bonding, whereby, finally, a highly reliable and accurate bonding state can be achieved.
    Type: Application
    Filed: February 19, 2003
    Publication date: September 11, 2003
    Inventors: Tadatomo Suga, Akira Yamauchi, Yoshiyuki Arai, Chisa Inaka
  • Publication number: 20030164396
    Abstract: A mounting method for bonding a first object having a metal joint part to a second object, comprising the steps of cleaning at least the surface of the metal joint part of the first object by irradiating an energy wave or energy particle beam, and thermally bonding the cleaned metal joint part of the first object to a portion to be bonded of the second object by heating in a special gas atmosphere, and a device thereof. In the mounting, the primary and secondary oxidations of the metal joint part can be efficiently prevented, and thereby highly reliable bonding can be carried out.
    Type: Application
    Filed: February 19, 2003
    Publication date: September 4, 2003
    Inventors: Tadatomo Suga, Akira Yamauchi