Patents by Inventor Tadatomo Suga

Tadatomo Suga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030164394
    Abstract: A mounting apparatus for bonding objects to each other, comprising a cleaning part (3) for cleaning at least the bonding surfaces of first objects (2a, 2b) and a bonding part (4) for bonding the cleaned first objects (2a, 2b) to a second object (2c), wherein both parts are connected to each other so that the objects can be conveyed between both parts, and an inverting mechanism (17) for turning over the first objects (2a, 2b) without touching the cleaned bonding surfaces is provided in the bonding part, whereby the cleaning of the bonding surfaces can be carried out efficiently, and a total time for a series of operations ranging from the cleaning to the completion of bonding can be shortened remarkably.
    Type: Application
    Filed: February 19, 2003
    Publication date: September 4, 2003
    Inventors: Tadatomo Suga, Akiro Yamaguchi
  • Publication number: 20030155662
    Abstract: A method of efficiently and inexpensively fabricating a chip-size package having an electrode pitch expanded by forming a conductor wiring on the electrode forming surface side of a semiconductor chip, especially, a method for facilitating wiring and bump forming. A semiconductor device comprising a semi-conductor elements and conductor wirings formed on the semiconductor elements by etching wiring-forming metal foil; and a fabrication method for a semiconductor device comprising the steps of laminating wiring forming metal foil on the electrode forming surface side on the semiconductor, forming a resist wiring pattern on the metal foil, etching the metal foil, and slicing the device into individual elements.
    Type: Application
    Filed: February 28, 2003
    Publication date: August 21, 2003
    Inventors: Kinji Saijo, Shingji Ohsawa, Hiroaki Okamoto, Kazuo Yoshida, Tadatomo Suga
  • Patent number: 6472293
    Abstract: In a multi-layer interconnection structure, the wiring length is to be reduced, and the interconnection is to be straightened, at the same time as measures need to be taken against radiation noise. To this end, there is disclosed a semiconductor device in which plural semiconductor substrates, each carrying semiconductor elements, are bonded together. On each semiconductor substrate is deposited an insulating layer through which is formed a connection wiring passed through the insulating layer so as to be connected to the interconnection layer of the semiconductor element. On a junction surface of at least one of the semiconductor substrates is formed an electrically conductive layer of an electrically conductive material in which an opening is bored in association with the connection wiring. The semiconductor substrates are bonded together by the solid state bonding technique to interconnect the connection wirings formed on each semiconductor substrate.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: October 29, 2002
    Assignees: Oki Electric Industry Co., Ltd., Sanyo Electric Co., Ltd., Sony Corporation, Kabushiki Kaisha Toshiba, NEC Corporation, Sharp Kabushiki Kaisha, Hitachi, Ltd., Fujitsu Limited, Matsushita Electronics Corporation, Mitsubishi Denki Kabushiki Kaisha, Rohm Co., Ltd.
    Inventor: Tadatomo Suga
  • Patent number: 6465892
    Abstract: In a multi-layer interconnection structure, the wiring length is to be reduced, and the interconnection is to be straightened, at the same time as measures need to be taken against radiation noise. To this end, there is disclosed a semiconductor device in which plural semiconductor substrates, each carrying semiconductor elements, are bonded together. On each semiconductor substrate is deposited an insulating layer through which is formed a connection wiring passed through the insulating layer so as to be connected to the interconnection layer of the semiconductor element. On a junction surface of at least one of the semiconductor substrates is formed an electrically conductive layer of an electrically conductive material in which an opening is bored in association with the connection wiring. The semiconductor substrates are bonded together by the solid state bonding technique to interconnect the connection wirings formed on each semiconductor substrate.
    Type: Grant
    Filed: April 13, 2000
    Date of Patent: October 15, 2002
    Assignees: Oki Electric Industry Co., Ltd., Sanyo Electric Co., Ltd., Sony Corporation, Kabushiki Kaisha Toshiba, NEC Corporation, Sharp Kabushiki Kaisha, Hitachi, Ltd., Fujitsu Limited, Matsushita Electronics Corporation, Mitsubishi Denki Kabushiki Kaisha, Rohm Co., Ltd.
    Inventor: Tadatomo Suga
  • Publication number: 20020074670
    Abstract: In a multi-layer interconnection structure, the wiring length is to be reduced, and the interconnection is to be straightened, at the same time as measures need to be taken against radiation noise. To this end, there is disclosed a semiconductor device in which plural semiconductor substrates, each carrying semiconductor elements, are bonded together. On each semiconductor substrate is deposited an insulating layer through which is formed a connection wiring passed through the insulating layer so as to be connected to the interconnection layer of the semiconductor element. On a junction surface of at least one of the semiconductor substrates is formed an electrically conductive layer of an electrically conductive material in which an opening is bored in association with the connection wiring. The semiconductor substrates are bonded together by the solid state bonding technique to interconnect the connection wirings formed on each semiconductor substrate.
    Type: Application
    Filed: November 30, 2001
    Publication date: June 20, 2002
    Inventor: Tadatomo Suga
  • Publication number: 20020021142
    Abstract: Disclosed is an inspection method for inspecting the electrical characteristics of a device by bringing an inspecting probe into electrical contact with an inspection electrode. An insulating film formed on the surface of the inspection electrode is broken by utilizing a fritting phenomenon so as to bring the inspection electrode into electrical contact with the inspection electrode.
    Type: Application
    Filed: August 20, 2001
    Publication date: February 21, 2002
    Inventors: Shinji Iino, Kiyoshi Takekoshi, Tadatomo Suga, Toshihiro Itoh, Kenichi Kataoka
  • Publication number: 20020003307
    Abstract: There are provided a semiconductor device and method for fabricating the device capable of achieving reliable electrical connection by securely directly bonding conductors to each other even though bonding surfaces are polished by a CMP method and solid-state-bonded to each other. By polishing according to the CMP method, a through hole conductor 5 and a grounding wiring layer 10, which are made of copper, become concave in a dish-like shape and lowered in level, causing a dishing portion 17 since they have a hardness lower than that of a through hole insulator 11 made of silicon nitride. The through hole insulator 11 is selectively etched by a reactive ion etching method until the through hole insulator 11 comes to have a height equal to the height of a bottom portion 19 of the dishing portion 17 of the through hole conductor 5. The through hole conductors 5 and 25 are aligned with each other, and the bonding surfaces 12 and 22 are bonded to each other in a solid state bonding manner.
    Type: Application
    Filed: July 5, 2001
    Publication date: January 10, 2002
    Inventor: Tadatomo Suga