Abstract: Disclosed herein are a method for access control using real-time positioning technology and a device using the same. According to a positioning method of a positioning module, the positioning module is configured to measure a location of at least one location-unrecognized device and a location of a terminal, wherein the at least one location-unrecognized device, the terminal and at least one location-recognized device is located in a certain zone, and wherein the positioning module has coordinate information of the at least one location-recognized device and the positioning module has not coordinate information of the at least one location-unrecognized device.

Abstract: An manufacturing method of a display device may include the following steps: forming a transistor on a substrate; forming an insulating layer on the transistor; forming a conductive layer including silver on the insulating layer; forming a photosensitive member on the conductive layer; forming an electrode of a light-emitting element by etching the conductive layer; performing plasma treatment on a structure that comprises the electrode, the plasma treatment using a gas including a halogen; and removing a product that is resulted from the plasma treatment.

Abstract: The present disclosure discloses a substrate heat-treating apparatus including a process chamber in which a flat substrate to be heat treated is placed, the process chamber comprising a beam transmitting plate placed below the flat substrate and an infrared transmitting plate placed above the flat substrate; a beam irradiating module for irradiating a VCSEL beam having a single wavelength to a lower surface of the flat substrate through the beam transmitting plate; and an emissivity measuring configured to measure the laser beam reflected from the lower surface or an upper surface the flat substrate, thereby measuring the emissivity of the flat substrate.

Abstract: A fan-out semiconductor package includes connection pads of a semiconductor chip that are redistributed and electrically connected to connection terminals by an interconnection member. In the fan-out semiconductor package, disposition forms of vias and pads in the interconnection member are designed so that stress may be reduced, such that reliability is improved.

Abstract: A fan-out semiconductor package includes connection pads of a semiconductor chip that are redistributed and electrically connected to connection terminals by an interconnection member. In the fan-out semiconductor package, disposition forms of vias and pads in the interconnection member are designed so that stress may be reduced, such that reliability is improved.

Abstract: Disclosed are substrates having an electronic component, including a frame having a through hole, the electronic component disposed in the through hole, a first wiring portion formed on a surface of the frame and the electronic component, a first layer formed on the first wiring portion, and a second wiring portion formed on the first layer, and the second wiring portion including an antenna layer.

Abstract: A fan-out semiconductor package includes connection pads of a semiconductor chip that are redistributed and electrically connected to connection terminals by an interconnection member. In the fan-out semiconductor package, disposition forms of vias and pads in the interconnection member are designed so that stress may be reduced, such that reliability is improved.

Abstract: A semiconductor package includes a semiconductor chip; a connection member having a first surface on which the semiconductor chip is disposed and a second surface opposing the first surface, an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip, a passivation layer on the second surface of the connection member; and an UBM layer partially embedded in the passivation layer, wherein the UBM layer includes an UBM via embedded in the passivation layer and connected to the redistribution layer of the connection member and an UBM pad connected to the UBM via and protruding from a surface of the passivation layer, and a width of a portion of the UBM via in contact with the UBM pad is narrower than a width of a portion of the UBM via in contact with the redistribution layer.

Abstract: A fan-out semiconductor package includes connection pads of a semiconductor chip that are redistributed and electrically connected to connection terminals by an interconnection member. In the fan-out semiconductor package, disposition forms of vias and pads in the interconnection member are designed so that stress may be reduced, such that reliability is improved.

Abstract: A semiconductor package including an organic interposer includes: a semiconductor chip; a connection member on the semiconductor chip and including a pad layer, a redistribution layer, and an insulating layer; a bonding member between the semiconductor chip and the pad layer; a surface treatment layer on the pad layer and including at least one metal layer; and an under-bump metallurgy (UBM) layer embedded in the connection member. The UBM layer includes a UBM pad, at least one plating layer on the UBM pad, and a UBM via. The surface treatment layer is disposed only on one surface of the pad layer, the plating layer are is disposed only on one surface of the UBM pad, and at least a portion of a side surface of the plating layer is spaced apart from a side surface of the insulating layer surrounding the plating layer.

Abstract: A carrier substrate comprises a core layer, a first metal layer disposed on the core layer, a release layer disposed on the first metal layer, and a second metal layer disposed on the release layer. At least one layer among the first metal layer, the release layer, and the second metal layer is disposed in a plurality of unit pattern portions having an area smaller than an area of the core layer. In addition, a method of manufacturing a semiconductor package using the carrier substrate is provided.

Abstract: A semiconductor package includes a semiconductor chip; a connection member having a first surface on which the semiconductor chip is disposed and a second surface opposing the first surface, an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip, a passivation layer on the second surface of the connection member; and an UBM layer partially embedded in the passivation layer, wherein the UBM layer includes an UBM via embedded in the passivation layer and connected to the redistribution layer of the connection member and an UBM pad connected to the UBM via and protruding from a surface of the passivation layer, and a width of a portion of the UBM via in contact with the UBM pad is narrower than a width of a portion of the UBM via in contact with the redistribution layer.

Abstract: A fan-out semiconductor package includes connection pads of a semiconductor chip that are redistributed and electrically connected to connection terminals by an interconnection member. In the fan-out semiconductor package, disposition forms of vias and pads in the interconnection member are designed so that stress may be reduced, such that reliability is improved.

Abstract: A semiconductor package includes a semiconductor chip; a connection member having a first surface on which the semiconductor chip is disposed and a second surface opposing the first surface, an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip, a passivation layer on the second surface of the connection member; and an UBM layer partially embedded in the passivation layer, wherein the UBM layer includes an UBM via embedded in the passivation layer and connected to the redistribution layer of the connection member and an UBM pad connected to the UBM via and protruding from a surface of the passivation layer, and a width of a portion of the UBM via in contact with the UBM pad is narrower than a width of a portion of the UBM via in contact with the redistribution layer.

Abstract: A fan-out semiconductor package includes connection pads of a semiconductor chip that are redistributed and electrically connected to connection terminals by an interconnection member. In the fan-out semiconductor package, disposition forms of vias and pads in the interconnection member are designed so that stress may be reduced, such that reliability is improved.

Abstract: A fan-out sensor package includes: a first interconnection member having a through-hole; a sensor disposed in the through-hole of the first interconnection member and having an active surface having connection pads and microlenses disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the active surface or the inactive surface of the sensor; and a second interconnection member disposed on the first interconnection member and the inactive surface or the active surface of the sensor. The first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the sensor. A camera module includes the fan-out sensor package.

Abstract: A semiconductor package including an organic interposer includes: a semiconductor chip; a connection member on the semiconductor chip and including a pad layer, a redistribution layer, and an insulating layer; a bonding member between the semiconductor chip and the pad layer; a surface treatment layer on the pad layer and including at least one metal layer; and an under-bump metallurgy (UBM) layer embedded in the connection member. The UBM layer includes a UBM pad, at least one plating layer on the UBM pad, and a UBM via. The surface treatment layer is disposed only on one surface of the pad layer, the plating layer are is disposed only on one surface of the UBM pad, and at least a portion of a side surface of the plating layer is spaced apart from a side surface of the insulating layer surrounding the plating layer.

Abstract: A fan-out sensor package includes: a first interconnection member having a through-hole; a sensor disposed in the through-hole of the first interconnection member and having an active surface having connection pads and microlenses disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the active surface or the inactive surface of the sensor; and a second interconnection member disposed on the first interconnection member and the inactive surface or the active surface of the sensor. The first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the sensor. A camera module includes the fan-out sensor package.

Abstract: An acoustic wave device includes an acoustic wave generator spaced apart from a support layer and disposed on a substrate; a protective member coupled to the support layer and spaced apart from the acoustic wave generator by a predetermined distance; and a sealing component sealing the protective member.

Abstract: A carrier substrate comprises a core layer, a first metal layer disposed on the core layer, a release layer disposed on the first metal layer, and a second metal layer disposed on the release layer. At least one layer among the first metal layer, the release layer, and the second metal layer is disposed in a plurality of unit pattern portions having an area smaller than an area of the core layer. In addition, a method of manufacturing a semiconductor package using the carrier substrate is provided.