Abstract: An electronic device module and method thereof include a first device, a rewiring part, and second devices. The first device is mounted on a surface of a board. The rewiring part is formed along the surface of the board and a contour of the first device. The second devices are mounted on the rewiring part.

Abstract: An apparatus for manufacturing a semiconductor package module and a method of manufacturing a semiconductor package are provided. The apparatus for manufacturing a semiconductor package module includes a lower mold installed thereon with a board with at least one element mounted thereon, an upper mold, in a state of accommodating the board, provided above the board, a filler supplier disposed in at least one of the upper mold and the lower mold, and supplying a filler to a molding space between the board and the upper mold, and a pattern forming member provided in an inner surface of the upper mold that provides an uneven pattern on a molded part.

Abstract: Disclosed herein are a sensor package and a method of manufacturing the same. According to the embodiment of the present invention, a sensor package includes: a metal frame; a sensor chip formed on the metal frame and including a sensing part; a protective layer formed on the sensor chip and formed on remaining portions except for the sensing part; and a molding part formed to cover the metal frame and the sensor chip, wherein an upper surface of the protective layer and an upper surface of the molding part are disposed on the same surface.

Abstract: Disclosed herein are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a molding member having a cavity formed therein; a device mounted in the cavity; an insulating member formed inside the cavity and on and/or beneath the molding member and the device; a circuit layer formed on the insulating member, and including vias and connection pads electrically connected with the device; a solder resist layer formed on the circuit layer, and having openings exposing upper portions of the connection pads; and solder balls formed in the openings.

Abstract: The present invention relates to a chip embedded printed circuit board and a manufacturing method thereof and provides a chip embedded printed circuit board including: an insulating layer having vias formed therethrough; a first chip and a second chip embedded in the insulating layer and having pads, which are respectively exposed to upper and lower surfaces of the insulating layer, on one surfaces thereof; an upper pattern formed on the upper surface of the insulating layer to be connected to the pads of the first chip and the vias; and a lower pattern formed on the lower surface of the insulating layer to be connected to the pads of the second chip and the vias. Also, the present invention provides a manufacturing method of a chip embedded printed circuit board.

Abstract: Disclosed herein are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a molding member having a cavity formed therein; a device mounted in the cavity; an insulating member formed inside the cavity and on and/or beneath the molding member and the device; a circuit layer formed on the insulating member, and including vias and connection pads electrically connected with the device; a solder resist layer formed on the circuit layer, and having openings exposing upper portions of the connection pads; and solder balls formed in the openings.

Abstract: Embodiments of the invention provide a method of manufacturing an electronic component-embedded printed circuit board. The method includes the steps of providing a base plate, which has a cavity formed in a thickness direction thereof and to one side of which tape is adhered, and disposing an electronic component in the cavity, such that an active surface of the electronic component is flush with one side of the base plate. The method further includes forming an insulating material layer on the other side of the base plate to bury the electronic component, and removing the tape from the one side of the base plate and then forming a first circuit layer including connection patterns coming into contact with connecting terminals of the electronic component on the one side of the base plate.

Abstract: An embedded printed circuit board (PCB) includes: a copper foil laminate; an internal electronic component inserted into the copper foil laminate; a first circuit pattern formed on a surface of the internal electronic component; and a second circuit pattern formed on the copper foil laminate.

Abstract: A printed circuit board that include: an electronic component having a plating electrode pad having a predetermined thickness; an insulating resin layer that exposes a lower surface of the electrode pad, receives the electronic component, and embodies the electronic component so that the center of the base body forming the electronic component is positioned at the center of the insulating resin layer; and circuit layers that include a circuit pattern disposed on the electrode pad, form inter-layer connection, and are disposed on both surfaces of the insulating resin layer, respectively, the plating electrode pad having a thickness that conforms to a thickness from an upper surface of the electronic component to an upper surface of the insulating resin.

Abstract: Disclosed herein are an embedded ball grid array substrate and a manufacturing method thereof. The embedded ball grid array includes: a core layer having a cavity therein; a semiconductor device embedded in the cavity of the core layer; a first circuit layer having a circuit pattern including a wire bonding pad formed thereon; a second circuit layer having a circuit pattern including a solder ball pattern formed thereon; and a wire electrically connecting the semiconductor device to the wire bonding pad.

Abstract: Disclosed herein are an embedded ball grid array substrate and a manufacturing method thereof. The embedded ball grid array includes: a core layer having a cavity therein; a semiconductor device embedded in the cavity of the core layer; a first circuit layer having a circuit pattern including a wire bonding pad formed thereon; a second circuit layer having a circuit pattern including a solder ball pattern formed thereon; and a wire electrically connecting the semiconductor device to the wire bonding pad.

Abstract: Disclosed herein are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a molding member having a cavity formed therein; a device mounted in the cavity; an insulating member formed inside the cavity and on and/or beneath the molding member and the device; a circuit layer formed on the insulating member, and including vias and connection pads electrically connected with the device; a solder resist layer formed on the circuit layer, and having openings exposing upper portions of the connection pads; and solder balls formed in the openings.

Abstract: Disclosed herein are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a molding member having a cavity formed therein; a device mounted in the cavity; an insulating member formed inside the cavity and on and/or beneath the molding member and the device; a circuit layer formed on the insulating member, and including vias and connection pads electrically connected with the device; a solder resist layer formed on the circuit layer, and having openings exposing upper portions of the connection pads; and solder balls formed in the openings.

Abstract: Disclosed herein is a semiconductor package including an electrical device having a first lateral surface; and a core substrate including a cavity in which the electrical device is positioned, wherein the core substrate is inclined in a thickness direction of the core substrate and has a second lateral surface that defines the cavity.

Abstract: Disclosed herein is an embedded printed circuit board (PCB) including: a copper foil laminate; an internal electronic component inserted into the copper foil laminate; a first circuit pattern formed on a surface of the internal electronic component; and a second circuit pattern formed on the copper foil laminate. Since the surface space of the electronic component embedded in the substrate is utilized as a wiring space, a wiring design can be optimized, layers can be simplified, and an increase in the thickness of the substrate can be prevented. Also, malfunction of the embedded electronic component or a warping phenomenon of a PCB due to generated heat can be prevented.

Abstract: Provided are a substrate with built-in electronic component and a method for manufacturing the same. The method for manufacturing a substrate with built-in electronic component includes: forming conductive temporary bumps which penetrate and protrude through a prepreg sheet; mounting and attaching an electronic component on the protruding temporary bumps; forming an embedded substrate by laminating other prepreg sheet on the attached electronic component layer, laminating a metal sheet on a bottom of a laminate or on a bottom and top of the laminate, and pressing the prepreg sheets and the metal sheet; forming contact grooves by removing partial regions of the metal sheet and by removing the temporary bumps exposed by the removal of the metal sheet regions; and filling the contact grooves with a conductive metal and forming a circuit pattern.

Abstract: The present invention relates to a chip embedded printed circuit board and a manufacturing method thereof. The present invention provides the chip embedded printed circuit board including an insulating layer embedding a chip provided with posts at an upper part, vias formed through the insulating layer, upper patterns formed at the upper part of the insulating layer to be connected to the posts and the vias and lower patterns formed at a lower part of the insulating layer to be connected to the vias, and the manufacturing method thereof.

Abstract: Disclosed is a printed circuit board having an embedded electronic component, which includes a first insulating layer, an electronic component disposed in an opening formed in a thickness direction of the first insulating layer and having a metal bump, a polymer layer formed on one side of the first insulating layer and on which the electronic component is seated so that the metal bump of the electronic component perforates the polymer layer, a second insulating layer formed on the other side of the first insulating layer so as to embed the electronic component, a first circuit layer formed on the second insulating layer, and a second circuit layer formed on the polymer layer so as to be directly electrically connected to the metal bump that perforates the polymer layer, and in which roughness is formed on the polymer layer so that the force of adhesion of the polymer layer to a plating layer is enhanced, thus ensuring reliability of the electrical connection of a circuit layer which is subsequently formed.

Abstract: Disclosed herein are an embedded ball grid array substrate and a manufacturing method thereof. The embedded ball grid array includes: a core layer having a cavity therein; a semiconductor device embedded in the cavity of the core layer; a first circuit layer having a circuit pattern including a wire bonding pad formed thereon; a second circuit layer having a circuit pattern including a solder ball pattern formed thereon; and a wire electrically connecting the semiconductor device to the wire bonding pad.

Abstract: A method for manufacturing a stacked integrated circuit and package system includes: attaching a high temperature resistant layer on a top substrate; mounting a first top integrated circuit on the high temperature resistant layer; mounting a second top integrated circuit on the first top integrated circuit; molding an encapsulant over the first top integrated circuit, the second top integrated circuit and the top substrate; mounting a third top integrated circuit over the first top integrated circuit on a surface opposite the second top integrated circuit; mounting a fourth top integrated circuit on the third top integrated circuit; molding an encapsulant over the third top integrated circuit, the fourth top integrated circuit and the top substrate; forming top electrical connectors on a lower surface of the top substrate; and mounting a bottom package to the top electrical connectors.