Abstract: An integrated circuit package system is provided including forming a first substrate, mounting a first integrated circuit to the first substrate, and forming first planar interconnects in contact with the first integrated circuit and electrically connecting the first integrated circuit to the first substrate.

Abstract: Disclosed is a method for enhancing fatigue strength of a gear by producing compressive residual stress on a gear surface using shot peening. In the method according to the present invention, a plurality of shot balls are projected in a direction parallel to a straight line connecting a contact point of a root circle and an involute curve of a gear tooth to be subjected to the peening to a contact point of a tooth face circle and an involute curve of a gear tooth adjacent to the gear tooth to be subjected to the peening, and particularly a direction forming an angle of 0° to 15° relative to the straight line by use of high-pressure air.

Abstract: Disclosed is a packaged integrated circuit device with high heat dissipation performance and low weight. The packaged integrated circuit device includes an interconnection substrate having at least one layer of conductive trace material and at least one layer of insulating material and also having a first surface and a second surface disposed opposite to the first surface and having a plurality of electrical contacts formed on the second surface. At least one metal thermal conductive layer having a first surface is attached on the first surface of the interconnection substrate and having a second surface exposed to an exterior. A through hole region is formed in the interconnection substrate and the thermal conductive layer. An integrated circuit chip having a first surface exposed to an exterior and having also a second surface with a plurality of bond pads, opposite to the first surface of the integrated circuit chip, is placed within the through hole region.

Abstract: A semiconductor temperature detecting circuit is provided having a plurality of pairs of a MOS transistor for supplying current and a polycrystalline silicon resistor connected in series thereto. Each such pair is connected in between a first and a second power supply line. The voltage across the terminals of each polycrystalline silicon resistor is converted to a digital logic value and the combination of all such digital outputs represents the detected temperature. Each current supply transistor has its gate electrode connected to a common circuit which sets the current supply. The current setting circuit includes two p-channel MOS transistors and two n-channel MOS transistors. Each p-channel transistor in the current setting circuit has a current electrode connected to one power supply line and another current electrode connected to a current electrode of a corresponding n-channel transistor. Each n-channel transistor has its other current electrode connected to the other power supply line.

Abstract: A TTL to CMOS buffer includes a PMOS transistor and an NMOS transistor connected in series between Vcc and Vss. The buffer input is applied to the gate of both the PMOS and the NMOS transistor, and the buffer output is provided from the point of connection between the PMOS and the NMOS transistor. At least one other PMOS transistor has one current electrode connected to Vcc and a current electrode connected by a switch to the point of connection between the first PMOS and the NMOS transistor. At least one NMOS transistor has one current electrode connected to VSS and a current electrode connected by another switch to the point of connection between the first PMOS and the first NMOS transistor. Each switch is controlled by respective control signal generated by a temperature detecting circuit; each control signal is indicative of whether the device temperature is above or below a different predetermined level.