Abstract: A method for fabricating semiconductor device includes forming a nitride pattern and a hard mask pattern over a substrate, forming a trench by etching the substrate using the hard mask pattern as an etch barrier, forming an oxide layer filling the trench, performing a planarization process on the oxide layer until the nitride pattern is exposed, and removing the nitride pattern though a dry strip process using a plasma.

Abstract: A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation regions; gate patterns formed in a step structure over a border region between individual first active regions and second active region, wherein one side of the individual gate pattern is formed over a portion of the individual first active region, and the other side of the individual gate pattern is formed over a portion of the second active region; spacers formed on lateral walls of the gate patterns; first cell junction regions formed in the first active regions, for connecting to storage nodes; and a second cell junction region formed in the second active region, for connecting to a bit line.

Abstract: A method includes forming a photoresist pattern over a certain portion of a material layer to expose an ion implantation region, implanting impurities in the ion implantation region of the material layer using the photoresist pattern as an ion implantation barrier, and removing the photoresist pattern using plasma of a gas mixture including a hydrocarbon-based gas.

Abstract: A chip on glass type liquid crystal display device and a method for fabricating the same are provided in which a surface of a pad electrode for attaching a flexible printed circuit film is embossed to increase an adhesive force between a pad electrode and a flexible printed circuit film, thereby ensuring contact between the pad electrode and the flexible printed circuit film. Unit pixels in an active region contain thin film transistors formed at intersections of gate lines and data lines. A pad electrode is formed in an inactive region. An embossing pattern is formed on the pad electrode. An adhesive is provided on the pad electrode including the embossing pattern and an external drive circuit part is connected to the pad electrode by the adhesive.

Abstract: A pad oxide layer is formed on a substrate. A pad nitride layer is formed on the pad oxide layer. The pad nitride layer and the pad oxide layer are patterned. Predetermined portions of the substrate are etched using the pad nitride layer as an etch barrier to thereby form trenches used as device isolation regions. The trenches are filled with an insulation layer to thereby form device isolation regions. The pad nitride layer is removed. Recesses are formed by etching predetermined portions of the pad oxide layer and the substrate. The pad oxide layer is removed. A gate oxide layer is formed on the recesses and on the substrate. Gate structures of which bottom portions are buried in the recesses on the gate oxide layer are formed.

Abstract: A method of fabricating a recess channel in a semiconductor device includes forming a hard mask pattern over a substrate, etching the substrate using the hard mask pattern to form first recesses, forming an insulation layer over the hard mask pattern and the first recesses, etching the insulation layer to form spacers on sidewalls of the first recesses and on sidewalls of the hard mask pattern, etching the substrate below the first recesses to form second recesses using a sulfur fluoride containing gas mixture, and removing the hard mask pattern and the spacers.

Abstract: A method for fabricating a semiconductor device with a gate is provided. The method includes: forming a gate insulation layer over a substrate; sequentially forming a polysilicon layer, a silicide layer and a hard mask layer over the gate insulation layer; selectively patterning the hard mask layer; etching the silicide layer using the patterned hard mask layer as a mask such that the silicide layer has a cross-sectional etch profile that is negatively sloped; etching the polysilicon layer using the patterned hard mask layer as a mask to form a gate; and performing a light oxidation process to oxidize exposed sidewalls of the polysilicon layer and the silicide layer.

Abstract: A chip on glass type liquid crystal display device and a method for fabricating the same are provided in which a surface of a pad electrode for attaching a flexible printed circuit film is embossed to increase an adhesive force between a pad electrode and a flexible printed circuit film, thereby ensuring contact between the pad electrode and the flexible printed circuit film. Unit pixels in an active region contain thin film transistors formed at intersections of gate lines and data lines. A pad electrode is formed in an inactive region. An embossing pattern is formed on the pad electrode. An adhesive is provided on the pad electrode including the embossing pattern and an external drive circuit part is connected to the pad electrode by the adhesive.

Abstract: A chip on glass type liquid crystal display device and a method for fabricating the same are provided in which a surface of a pad electrode for attaching a flexible printed circuit film is embossed to increase an adhesive force between a pad electrode and a flexible printed circuit film, thereby ensuring contact between the pad electrode and the flexible printed circuit film. Unit pixels in an active region contain thin film transistors formed at intersections of gate lines and data lines. A pad electrode is formed in an inactive region. An embossing pattern is formed on the pad electrode. An adhesive is provided on the pad electrode including the embossing pattern and an external drive circuit part is connected to the pad electrode by the adhesive.

Abstract: A method for fabricating a semiconductor device includes forming an organic bottom anti-reflective coating over an etch target layer, forming a photoresist pattern over the organic bottom anti-reflective coating, and etching the organic bottom anti-reflective coating using a sulfur-containing gas.

Abstract: A method for fabricating a semiconductor device includes forming an amorphous carbon layer over a substrate, forming a hard mask pattern over the amorphous carbon layer, and etching the amorphous carbon layer with an etching gas including sulfur (S) using the hard mask pattern as an etch barrier. Deformation of the amorphous carbon patterns is prevented by hardening the sidewalls of the amorphous carbon layer exposed during etching of the amorphous carbon layer. Therefore, when the etch target layer is etched with the amorphous carbon patterns having a vertical shape, pattern uniformity of the etch target pattern can be improved.

Abstract: A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation regions; gate patterns formed in a step structure over a border region between individual first active regions and second active region, wherein one side of the individual gate pattern is formed over a portion of the individual first active region, and the other side of the individual gate pattern is formed over a portion of the second active region; spacers formed on lateral walls of the gate patterns; first cell junction regions formed in the first active regions, for connecting to storage nodes; and a second cell junction region formed in the second active region, for connecting to a bit line.

Abstract: A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation regions; gate patterns formed in a step structure over a border region between individual first active regions and second active region, wherein one side of the individual gate pattern is formed over a portion of the individual first active region, and the other side of the individual gate pattern is formed over a portion of the second active region; spacers formed on lateral walls of the gate patterns; first cell junction regions formed in the first active regions, for connecting to storage nodes; and a second cell junction region formed in the second active region, for connecting to a bit line.

Abstract: A method for forming a trench includes providing a substrate, and forming the trench in the substrate using a gas containing chlorine (Cl2) gas as a main etch gas and SiFX gas as an additive gas, wherein a sidewall of the trench has a substantially vertical profile by virtue of reaction of the Cl2 gas and the SiFX gas.

Abstract: A method for fabricating a nonvolatile memory device includes forming a gate stack over a substrate, the gate stack including an aluminum oxide layer as a dielectric layer, and etching the aluminum oxide layer of the gate stack using a gas containing silicon.

Abstract: The present invention is a method for testing a contact open capable of effectively testing a contact open defect in an In-line as securing a mass productivity. The method includes the steps of: performing a photolithography process for forming a contact; forming a contact hole by performing a contact etching process after sampling at least one wafer; depositing a conductive layer on the wafer provided with the contact hole; isolating the conductive layer within the contact hole; performing a test for testing a contact open interface to check whether a remaining layer is existed in an interface between the conductive layer and a lower structure of the conductive layer; and performing a process for etching the contact of a main lot based on a test result.

Abstract: A method for fabricating a semiconductor device includes providing a substrate, forming a sacrificial oxide layer over the substrate, the sacrificial layer having a higher etch rate than the substrate, forming a hard mask pattern over the sacrificial oxide layer, wet-etching the sacrificial oxide layer using the hard mask pattern as an etch barrier, and forming a recess by etching an exposed substrate using the hard mask pattern as an etch barrier.

Abstract: A method for fabricating a semiconductor device includes providing a substrate having a first and a second region, forming an etch target layer over the substrate, forming a hard mask layer over the etch target layer to have different thicknesses over the first and the second regions, forming a hard mask pattern by etching the hard mask layer, and etching the etch target layer using the hard mask pattern as an etch mask to form a target pattern having different densities over the first and the second regions.

Abstract: The semiconductor device includes a substrate including a first active region and a second active region having a greater height than that of the first active region. A gate pattern has a step structure, which is formed on a border region between the first active region and the second active region. The gate pattern extends from a predetermined portion of the first active region to a predecided portion of the second active region. Gate spacers are formed on both sidewalls of the gate pattern. A first cell junction is formed in the first active region at one gate spacer and connected to a storage node contact. A second cell junction is formed in the second active region at the other gate spacer and connected to a bit line contact.

Abstract: Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.