Abstract: A method includes forming a photoresist pattern over a certain portion of a material layer to expose an ion implantation region, implanting impurities in the ion implantation region of the material layer using the photoresist pattern as an ion implantation barrier, and removing the photoresist pattern using plasma of a gas mixture including a hydrocarbon-based gas.

Abstract: A method for fabricating a transistor of a semiconductor device is provided. The method includes: forming device isolation layers in a substrate including a bottom structure, thereby defining an active region; etching the active region to a predetermined depth to form a plurality of recess structures each of which has a flat bottom portion with a critical dimension (CD) larger than that of a top portion; and sequentially forming a gate oxide layer and a metal layer on the recess structures; and patterning the gate oxide layer and the metal layer to form a plurality of gate structures.

Abstract: A method of fabricating a recess channel in a semiconductor device includes forming a hard mask pattern over a substrate, etching the substrate using the hard mask pattern to form first recesses, forming an insulation layer over the hard mask pattern and the first recesses, etching the insulation layer to form spacers on sidewalls of the first recesses and on sidewalls of the hard mask pattern, etching the substrate below the first recesses to form second recesses using a sulfur fluoride containing gas mixture, and removing the hard mask pattern and the spacers.

Abstract: Semiconductor manufacturing processes that reduce production costs as well as increase throughput by substituting the PR strip and ACT wet cleaning procedure after the via contact etching of a semiconductor with dry cleaning to be performed while removing a photoresist in a conventional PR strip apparatus. In addition, the methods can shorten waiting time and maintain consistency in the process by performing the PR strip and cleaning at the same time in the same chamber. The resultant devices have lower via contact resistance and its deviation, as compared to the conventional PR strip and ACT wet cleaning.

Abstract: A pad oxide layer is formed on a substrate. A pad nitride layer is formed on the pad oxide layer. The pad nitride layer and the pad oxide layer are patterned. Predetermined portions of the substrate are etched using the pad nitride layer as an etch barrier to thereby form trenches used as device isolation regions. The trenches are filled with an insulation layer to thereby form device isolation regions. The pad nitride layer is removed. Recesses are formed by etching predetermined portions of the pad oxide layer and the substrate. The pad oxide layer is removed. A gate oxide layer is formed on the recesses and on the substrate. Gate structures of which bottom portions are buried in the recesses on the gate oxide layer are formed.

Abstract: A method for fabricating a semiconductor device with a gate is provided. The method includes: forming a gate insulation layer over a substrate; sequentially forming a polysilicon layer, a silicide layer and a hard mask layer over the gate insulation layer; selectively patterning the hard mask layer; etching the silicide layer using the patterned hard mask layer as a mask such that the silicide layer has a cross-sectional etch profile that is negatively sloped; etching the polysilicon layer using the patterned hard mask layer as a mask to form a gate; and performing a light oxidation process to oxidize exposed sidewalls of the polysilicon layer and the silicide layer.

Abstract: Disclosed is a method for fabricating a semiconductor device without damaging a hard mask of a conductive structure. The method includes the steps of: forming a plurality of conductive structures on a substrate, each conductive structure including a conductive layer and a hard mask; sequentially forming a first nitride layer, an oxide layer, a second nitride layer, and an etch stop layer on the plurality of conductive structures; forming an inter-layer insulation layer on the etch stop layer; removing a portion of the inter-layer insulation layer through a planarization process; performing a self-aligned etching (SAC) process selectively etching the inter-layer insulation layer, the second nitride layer and the oxide layer until the SAC etching process is stopped at the first nitride layer to thereby form a contact hole exposing the first nitride layer; and removing the first nitride layer by performing a blanket etch-back process to thereby expose the conductive layer.

Abstract: A method for fabricating a transistor of a semiconductor device is provided. The method includes: forming device isolation layers in a substrate including a bottom structure, thereby defining an active region; etching the active region to a predetermined depth to form a plurality of recess structures each of which has a flat bottom portion with a critical dimension (CD) larger than that of a top portion; and sequentially forming a gate oxide layer and a metal layer on the recess structures; and patterning the gate oxide layer and the metal layer to form a plurality of gate structures.

Abstract: Disclosed is a method for fabricating a semiconductor device with an improved process margin obtained by preventing damage to an inter-layer insulation layer during a wet cleaning process. Particularly, the method includes the steps of: forming a plurality of a first conductive pattern having a stack pattern of a first conductive and a first hard mask; forming a first inter-layer insulation layer of a good gap-fill property with a height between the first conductive material and the first hard mask on the first conductive layer; forming a second inter-layer insulation layer; forming a second conductive layer contacted the first conductive layer between the plurality of the first conductive patterns as passing through the first and the second inter-layer insulation layers; forming a third inter-layer insulation layer; forming a plurality of second conductive patterns; forming a fourth inter-layer insulation layer; and forming a third conductive layer contacted to the second conductive layer.

Abstract: A method for fabricating a semiconductor device capable of preventing a hard mask from being lifted and patterns from being defective. Particularly, an inter-layer insulation layer and an etch stop layer formed on a substrate structure provided with conductive structures are first planarized. Then, a hard mask made of a nitride-based material is formed by using a photoresist pattern and an anti-reflective coating layer as an etch mask. After the hard mask formation, the photoresist pattern and the anti-reflective coating layer are removed. Subsequently, a SAC etching process is performed to etch the inter-layer insulation layer with use of the hard mask as an etch mask, thereby obtaining a contact hole exposing the etch stop layer disposed between the conductive structures. The exposed etch stop layer is removed through the use of a blanket etch-back process, and a cleaning process is applied thereafter.

Abstract: A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation regions; gate patterns formed in a step structure over a border region between individual first active regions and second active region, wherein one side of the individual gate pattern is formed over a portion of the individual first active region, and the other side of the individual gate pattern is formed over a portion of the second active region; spacers formed on lateral walls of the gate patterns; first cell junction regions formed in the first active regions, for connecting to storage nodes; and a second cell junction region formed in the second active region, for connecting to a bit line.

Abstract: The semiconductor device includes a substrate including a first active region and a second active region having a greater height than that of the first active region. A gate pattern has a step structure, which is formed on a border region between the first active region and the second active region. The gate pattern extends from a predetermined portion of the first active region to a predecided portion of the second active region. Gate spacers are formed on both sidewalls of the gate pattern. A first cell junction is formed in the first active region at one gate spacer and connected to a storage node contact. A second cell junction is formed in the second active region at the other gate spacer and connected to a bit line contact.

Abstract: Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.

Abstract: The present invention relates to a method for fabricating a recessed gate structure. The method includes the steps of: selectively etching a substrate to form a plurality of openings; forming a gate oxide layer on the openings and the substrate; forming a first conductive silicon layer on the gate oxide layer to form a plurality of valleys at a height equal to or greater than a thickness remaining after an intended pattern is formed; planarizing the first conductive silicon layer until the thickness remaining after the intended pattern formation is obtained, so that the valleys are removed; forming a second conductive layer on a planarized first conductive silicon layer; and selectively etching the second conductive layer, the first conductive silicon layer and the gate oxide layer to form a plurality of the recessed gate structures.

Abstract: Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.

Abstract: Disclosed is a method for fabricating a semiconductor device capable of preventing a depth of a plurality of moats M from getting deeper as preventing lowering a threshold voltage by forming a round shape of a top corner of a trench. Particularly, the method includes the steps of: forming a pad pattern by sequentially stacking a pad oxide layer and a pad nitride layer on a substrate; forming a trench by etching process to an exposed surface of the substrate by using the pad pattern as a mask; filling an insulation layer for isolating device elements filled into the trench; removing the pad nitride layer; performing a pre-cleaning process for removing the pad oxide layer; selectively recessing the surface of the substrate to remove a plurality of moats M taken place after removing the pad oxide layer; and forming a screen oxide layer on the surface of the substrate.

Abstract: Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.

Abstract: Disclosed are a semiconductor device with a three-dimensional storage node and a method for fabricating the same. The semiconductor device includes: an inter-layer insulation layer formed on a substrate; a first plug contacted to the substrate by penetrating into the inter-layer insulation layer; an insulation layer formed on the first plug; a second plug contacted to the first plug by penetrating into the insulation layer and projected in an upward direction from a surface level of the insulation layer; a barrier layer formed on the second plug and the insulation layer; and a storage node formed on the second plug to be connected with the second plug through a portion where the barrier layer is removed.

Abstract: Disclosed are a semiconductor device and a method for fabricating the same capable of preventing a bridge generation between plugs during forming a plurality of hole type contact plugs for forming storage nodes. The semiconductor device includes: a first gate structure and a second gate structure placed in parallel by a predetermined space; a plurality of bit lines placed on upper portions of the first gate structure and the second gate structure with crossing the first gate structure and the second gate structure; a first cell contact plug and a second cell contact plug located through the plurality of bit lines and formed between the first gate structure and the second gate structure; and an inter-layer insulation layer provided with a first storage node contact hole and a second storage node contact hole connected with each other by etching the inter-layer insulation layer on upper portions of the plurality of bit lines.

Abstract: The present invention is a method for testing a contact open capable of effectively testing a contact open defect in an In-line as securing a mass productivity. The method includes the steps of: performing a photolithography process for forming a contact; forming a contact hole by performing a contact etching process after sampling at least one wafer; depositing a conductive layer on the wafer provided with the contact hole; isolating the conductive layer within the contact hole; performing a test for testing a contact open interface to check whether a remaining layer is existed in an interface between the conductive layer and a lower structure of the conductive layer; and performing a process for etching the contact of a main lot based on a test result.