Abstract: Disclosed is a method for fabricating a semiconductor device capable of preventing a depth of a plurality of moats M from getting deeper as preventing lowering a threshold voltage by forming a round shape of a top corner of a trench. Particularly, the method includes the steps of: forming a pad pattern by sequentially stacking a pad oxide layer and a pad nitride layer on a substrate; forming a trench by etching process to an exposed surface of the substrate by using the pad pattern as a mask; filling an insulation layer for isolating device elements filled into the trench; removing the pad nitride layer; performing a pre-cleaning process for removing the pad oxide layer; selectively recessing the surface of the substrate to remove a plurality of moats M taken place after removing the pad oxide layer; and forming a screen oxide layer on the surface of the substrate.

Abstract: Disclosed is a method for fabricating a semiconductor device without damaging a hard mask of a conductive structure. The method includes the steps of: forming a plurality of conductive structures on a substrate, each conductive structure including a conductive layer and a hard mask; sequentially forming a first nitride layer, an oxide layer, a second nitride layer, and an etch stop layer on the plurality of conductive structures; forming an inter-layer insulation layer on the etch stop layer; removing a portion of the inter-layer insulation layer through a planarization process; performing a self-aligned etching (SAC) process selectively etching the inter-layer insulation layer, the second nitride layer and the oxide layer until the SAC etching process is stopped at the first nitride layer to thereby form a contact hole exposing the first nitride layer; and removing the first nitride layer by performing a blanket etch-back process to thereby expose the conductive layer.

Abstract: Disclosed is a method for fabricating a semiconductor device with an improved process margin obtained by preventing damage to an inter-layer insulation layer during a wet cleaning process. Particularly, the method includes the steps of: forming a plurality of a first conductive pattern having a stack pattern of a first conductive and a first hard mask; forming a first inter-layer insulation layer of a good gap-fill property with a height between the first conductive material and the first hard mask on the first conductive layer; forming a second inter-layer insulation layer; forming a second conductive layer contacted the first conductive layer between the plurality of the first conductive patterns as passing through the first and the second inter-layer insulation layers; forming a third inter-layer insulation layer; forming a plurality of second conductive patterns; forming a fourth inter-layer insulation layer; and forming a third conductive layer contacted to the second conductive layer.

Abstract: A method for fabricating a semiconductor device capable of preventing a hard mask from being lifted and patterns from being defective. Particularly, an inter-layer insulation layer and an etch stop layer formed on a substrate structure provided with conductive structures are first planarized. Then, a hard mask made of a nitride-based material is formed by using a photoresist pattern and an anti-reflective coating layer as an etch mask. After the hard mask formation, the photoresist pattern and the anti-reflective coating layer are removed. Subsequently, a SAC etching process is performed to etch the inter-layer insulation layer with use of the hard mask as an etch mask, thereby obtaining a contact hole exposing the etch stop layer disposed between the conductive structures. The exposed etch stop layer is removed through the use of a blanket etch-back process, and a cleaning process is applied thereafter.

Abstract: A method for fabricating a semiconductor device with a trench type device isolation layer capable of controlling a rounding angle of top corners of a trench and removing damaged layers formed after etching the trench. Particularly, the top corners of the trench is manipulated to have an angle of about 30° to about 60° by using a gas containing at least hydrogen bromide and chlorine gas. Then, an isotropic etching technique is performed as a light etch treatment to make the top corners have an angle of about 50° to about 80°. Finally, a dry oxidation technique is performed to form a screen oxide layer and a gate oxide layer so that moat generations are minimized prior to forming a gate electrode.

Abstract: Semiconductor manufacturing processes that reduce production costs as well as increase throughput by substituting the PR strip and ACT wet cleaning procedure after the via contact etching of a semiconductor with dry cleaning to be performed while removing a photoresist in a conventional PR strip apparatus. In addition, the methods can shorten waiting time and maintain consistency in the process by performing the PR strip and cleaning at the same time in the same chamber. The resultant devices have lower via contact resistance and its deviation, as compared to the conventional PR strip and ACT wet cleaning.

Abstract: An improved method for fabricating a capacitor capable of reducing defects introduced as a result of complicated processes required to separate the bottom electrodes of the capacitors is provided to thereby enhance the yield of the resulting semiconductor devices. The method comprises forming an insulating film on a substrate; selectively etching the insulating film to open regions for the formation of the bottom electrode; depositing a conductive layer on the substrate including the opened regions; forming a photoresist pattern; and then, preferably in a single etch chamber, completing the process by removing the conductive layer in the peripheral circuit region; etching back the photoresist pattern to expose the conductive layer in the cell region; etching back the conductive layer to form the bottom electrodes; and removing any residual photoresist.

Abstract: An improved method for fabricating a capacitor capable of reducing defects introduced as a result of complicated processes required to separate the bottom electrodes of the capacitors is provided to thereby enhance the yield of the resulting semiconductor devices. The method comprises forming an insulating film on a substrate; selectively etching the insulating film to open regions for the formation of the bottom electrode; depositing a conductive layer on the substrate including the opened regions; forming a photoresist pattern; and then, preferably in a single etch chamber, completing the process by removing the conductive layer in the peripheral circuit region; etching back the photoresist pattern to expose the conductive layer in the cell region; etching back the conductive layer to form the bottom electrodes; and removing any residual photoresist.

Abstract: A method for manufacturing a gate electrode, the method including the steps of forming upon a semiconductor substrate a polysilicon layer, a metal nitride layer, a tungsten layer and a photoresist layer, patterning the photoresist layer on the tungsten layer into a predetermined configuration, etching the tungsten layer, the metal nitride layer, a portion of the polysilicon layer into the predetermined configuration by using a mixed etchant of fluorine and chlorine species etchant, and patterning the remaining polysilicon layer into the predetermined configuration by using chlorine etchant.