Abstract: A semiconductor device includes a monitoring circuit suitable for generating a monitoring signal indicating whether a speed of a memory clock signal is changed based on a speed information signal representing speed information of the memory clock signal; a cycle control circuit suitable for generating a refresh cycle control signal for controlling a refresh cycle based on a system clock signal, the memory clock signal, the monitoring signal and a refresh flag signal; and a control circuit suitable for generating the memory clock signal and the refresh flag signal based on the speed information signal, the system clock signal and the refresh cycle control signal.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising a semiconductor die coupled to a substrate and surrounded by a perforated metal plane and a method of manufacturing thereof.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising one or more conductive shielding members and an EMI shielding layer, and a method of manufacturing thereof.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising multiple encapsulating layers and multiple signal distribution structures, and a method of manufacturing thereof.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a stackable semiconductor device with small size and fine pitch and a method of manufacturing thereof.

Abstract: A semiconductor device with EMI shield and a fabricating method thereof are provided. In one embodiment, the semiconductor device includes EMI shield on all six surfaces of the semiconductor device without the use of a discrete EMI lid.

Abstract: Provided are a semiconductor package and a manufacturing method thereof for securing a space for mounting a semiconductor device by etching a temporary metal plate to form a plurality of conductive posts.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising a semiconductor die coupled to a substrate and surrounded by a perforated metal plane and a method of manufacturing thereof.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a stackable semiconductor device with small size and fine pitch and a method of manufacturing thereof.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device, and a method of manufacturing thereof, that comprises a substrate including a dielectric layer, at least one conductive trace and conductive bump pad formed on one surface of the dielectric layer, and a protection layer covering the at least one conductive trace and conductive bump pad, the at least one conductive bump pad having one end exposed through the protection layer, and a semiconductor die electrically connected to the conductive bump pad of the substrate.

Abstract: Provided are a semiconductor package and a manufacturing method thereof for securing a space for mounting a semiconductor device by etching a temporary metal plate to form a plurality of conductive posts.

Abstract: A command generation circuit, test control circuit, semiconductor device, semiconductor system, and or a test method may be provided. The semiconductor device may be configured to enter test modes and to generate internal commands during a clock cycle.

Abstract: A command generation circuit, test control circuit, semiconductor device, semiconductor system, and or a test method may be provided. The semiconductor device may be configured to enter test modes and to generate internal commands during a clock cycle.

Abstract: A semiconductor apparatus may include: a data storage group including first to eight data storage areas; a first channel select pad configured to transmit a first channel select signal to the first and third data storage areas; a second channel select pad configured to transmit a second channel select signal to the second and fourth data storage areas; a third channel select pad configured to transmit the first channel select signal to the sixth and eighth data storage areas; a fourth channel select pad configured to transmit the second channel select signal to the fifth and seventh data storage areas; a first clock enable pad configured to transmit a first clock enable signal to the first and third data storage areas; a second clock enable pad configured to transmit a second clock enable signal to the second and fourth data storage areas; a third clock enable pad configured to transmit the first clock enable signal to the fifth and seventh data storage areas; and a fourth clock enable pad configured to trans

Abstract: A semiconductor package may include a first chip located over a substrate. The semiconductor package may include a second chip located over the substrate and adjacent to the first chip. The semiconductor package may include a test micro-bump located at a layer below the first chip and above the substrate, and electrically coupled to an external connection member through a first path. The semiconductor package may include a normal micro-bump located at a layer below the first chip and above the substrate, and electrically coupled to the second chip through a second path.

Abstract: Disclosed is a light emitting device including a light emitting structure including a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, and a second conductive semiconductor layer under the active layer, a first electrode electrically connected with the first conductive semiconductor layer, a mirror layer under the light emitting structure, a window semiconductor layer between the mirror layer and the light emitting structure, a reflective layer under the mirror layer, a conductive contact layer between the reflective layer and the window semiconductor layer and in contact with the second conductive semiconductor layer, and a conductive support substrate under the reflective layer. The window semiconductor layer includes a C-doped P-based semiconductor doped with a higher dopant concentration. The conductive contact layer includes material different from that of the mirror layer with a thickness thinner than that of the window semiconductor layer.

Abstract: A semiconductor device may include an input/output control signal generation circuit configured to generate at least one input control signal and at least one output control signal from a first control clock in response to a shifting control signal, a bank address latch circuit configured to generate a latch bank address signal by latching at least one bank address in response to the at least one input control signal and the at least one output control signal, a pipe latch circuit configured to generate an auto-precharge latch signal by latching an auto-precharge flag signal in response to the at least one input control signal and the at least one output control signal, and an auto-precharge signal generation circuit configured to generate at least one auto-precharge signal from the auto-precharge latch signal.

Abstract: Disclosed are a data training device and a semiconductor device. The data training device includes a write controller configured to align write data, a read controller configured to latch data applied from the write controller and sequentially output the latched data, and an offset compensator configured to adjust a current flowing through a power supply voltage application terminal and a ground voltage application terminal in correspondence to a write signal and a read signal, thereby compensating for an offset in the write controller and the read controller.

Abstract: A semiconductor package may include a first chip located over a substrate. The semiconductor package may include a second chip located over the substrate and adjacent to the first chip. The semiconductor package may include a test micro-bump located at a layer below the first chip and above the substrate, and electrically coupled to an external connection member through a first path. The semiconductor package may include a normal micro-bump located at a layer below the first chip and above the substrate, and electrically coupled to the second chip through a second path.

Abstract: A semiconductor apparatus may include: a data storage group including first to eight data storage areas; a first channel select pad configured to transmit a first channel select signal to the first and third data storage areas; a second channel select pad configured to transmit a second channel select signal to the second and fourth data storage areas; a third channel select pad configured to transmit the first channel select signal to the sixth and eighth data storage areas; a fourth channel select pad configured to transmit the second channel select signal to the fifth and seventh data storage areas; a first clock enable pad configured to transmit a first clock enable signal to the first and third data storage areas; a second clock enable pad configured to transmit a second clock enable signal to the second and fourth data storage areas; a third clock enable pad configured to transmit the first clock enable signal to the fifth and seventh data storage areas; and a fourth clock enable pad configured to trans