Abstract: A semiconductor chip includes an input pad and an output pad formed on the semiconductor chip; at least one bump formed on the semiconductor chip; and a test scan chain configured to output data applied from the input pad, to a node which is electrically coupled with the bump, store data corresponding to capacitance of the node by floating the node for a predetermined time, and output data corresponding to the stored capacitance, to the output pad.

Abstract: Disclosed is an air cleaner having independent fluid paths and a home appliance having the air cleaner. The air cleaner includes a front panel having a plurality of air inlets formed thereon for air to flow in from outside of the case, first and second blower devices arranged inside the case to allow air to flow in through the plurality of air inlets, first and second filter units arranged to filter the air flowing in by the first and second blower devices, a first outlet located on the case to release the air, a second outlet formed at a different location from that of the first outlet, a first fluid path formed between one of the plurality of air inlets and the first outlet; and a second fluid path formed between another of the plurality of air inlets and the second outlet.

Abstract: A semiconductor integrated circuit may include a plurality of semiconductor chips configured to be stacked in three dimensions, a first group of through-chip vias configured to go through the plurality of semiconductor chips, respectively, and to be used for density extension of the semiconductor integrated circuit, and a second group of through-chip vias configured to go through the plurality of semiconductor chips, respectively, and to be used for a bandwidth extension of the semiconductor integrated circuit. Each of the plurality of semiconductor chips includes a path selection unit configured to select one of the first group of through-chip vias arranged in the semiconductor chip or one of the second group of through-chip vias arranged in the semiconductor chip in response to a mode switching signal, and an internal circuit configured to be selectively coupled to a through-chip via selected by the path selection unit.

Abstract: A semiconductor integrated circuit includes a test bump pad, a first bump pad coupled to a first through-silicon-via (TSV), a second bump pad coupled to a second TSV, a latching unit, coupled between the test bump pad and the first bump pad, suitable for storing data, and a switching unit suitable for selectively coupling the first bump pad to the second bump pad in response to a test operation control signal.

Abstract: A test circuit of a semiconductor integrated circuit includes a through via, a voltage driving unit, and a determination unit. The through via is charged by receiving an input voltage. The voltage driving unit generates a test voltage by charging or discharging the through via in response to a test control signal. The determination unit compares levels of the input voltage and the test voltage and outputs a resultant signal.

Abstract: A semiconductor device includes a plurality of channels. Each of the channels includes a plurality of banks sequentially activated at intervals of a predetermined time in response to a refresh command; a comparator, when the refresh command is input to a corresponding channel, configured to detect whether the refresh command is applied to a contiguous channel; a delay decision unit configured to output a control signal to determine a bank active delay time in response to an output signal of the comparator; and a delay circuit configured to control an active delay time of the plurality of banks in response to an output signal of the delay decision unit.

Abstract: Disclosed is a light emitting device including a light emitting structure including a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, and a second conductive semiconductor layer under the active layer, a first electrode electrically connected with the first conductive semiconductor layer, a mirror layer under the light emitting structure, a window semiconductor layer between the mirror layer and the light emitting structure, a reflective layer under the mirror layer, a conductive contact layer between the reflective layer and the window semiconductor layer and in contact with the second conductive semiconductor layer, and a conductive support substrate under the reflective layer. The window semiconductor layer includes a C-doped P-based semiconductor doped with a higher dopant concentration. The conductive contact layer includes material different from that of the mirror layer with a thickness thinner than that of the window semiconductor layer.

Abstract: A semiconductor apparatus includes first and second through vias, a first path setting unit, and a second path setting unit. The first and second through vias connect first and second chips. The first path setting unit connects a first chip circuit to a first input/output terminal, and the second through via to a second input/output terminal. The second path setting unit connects a second chip circuit to the first through via and the second through via, wherein the first through via is connected to the second input/output terminal.

Abstract: A semiconductor chip includes an input pad and an output pad formed on the semiconductor chip; at least one bump formed on the semiconductor chip; and a test scan chain configured to output data applied from the input pad, to a node which is electrically coupled with the bump, store data corresponding to capacitance of the node by floating the node for a predetermined time, and output data corresponding to the stored capacitance, to the output pad.

Abstract: A test circuit of a semiconductor integrated circuit includes a through via, a voltage driving unit, and a determination unit. The through via is charged by receiving an input voltage. The voltage driving unit generates a test voltage by charging or discharging the through via in response to a test control signal. The determination unit compares levels of the input voltage and the test voltage and outputs a resultant signal.

Abstract: A semiconductor integrated circuit includes a test bump pad, a first bump pad coupled to a first through-silicon-via (TSV), a second bump pad coupled to a second TSV, a latching unit, coupled between the test bump pad and the first bump pad, suitable for storing data, and a switching unit suitable for selectively coupling the first bump pad to the second bump pad in response to a test operation control signal.

Abstract: A semiconductor apparatus includes first and second through vias, a first path setting unit, and a second path setting unit. The first and second through vias connect first and second chips. The first path setting unit connects a first chip circuit to a first input/output terminal, and the second through via to a second input/output terminal. The second path setting unit connects a second chip circuit to the first through via and the second through via, wherein the first through via is connected to the second input/output terminal.

Abstract: A semiconductor apparatus includes: a semiconductor chip, wherein a conductive layer is formed at one side of the semiconductor chip and one or more of probe pads are formed at the other side thereof; a plurality of through-silicon vias (TSVs), wherein one side of each of the plurality of TSVs is coupled to the conductive layer and the other side of one or more of the plurality of TSVs is coupled to the probe pad; a plurality of latch units each configured to be assigned to the plurality of corresponding TSVs and store a test signal, wherein the test signal is inputted via the probe pad and is transferred via the plurality of corresponding TSVs to the plurality of assigned latch units, respectively; and a signal combination unit configured to combine a plurality of signals stored in the plurality of latch units to output the result as an error detection signal.

Abstract: A semiconductor integrated circuit may include a plurality of semiconductor chips configured to be stacked in three dimensions, a first group of through-chip vias configured to go through the plurality of semiconductor chips, respectively, and to be used for density extension of the semiconductor integrated circuit, and a second group of through-chip vias configured to go through the plurality of semiconductor chips, respectively, and to be used for a bandwidth extension of the semiconductor integrated circuit. Each of the plurality of semiconductor chips includes a path selection unit configured to select one of the first group of through-chip vias arranged in the semiconductor chip or one of the second group of through-chip vias arranged in the semiconductor chip in response to a mode switching signal, and an internal circuit configured to be selectively coupled to a through-chip via selected by the path selection unit.

Abstract: In an aspect of the present invention, a semiconductor integrated circuit includes a semiconductor chip including a through-chip via, a probe pad disposed in such a way as not to overlap with the through-chip via, and a connection part electrically coupling the probe pad and the through-chip via

Abstract: A semiconductor memory apparatus includes a first pad group located along a first edge of a plurality of banks, a second pad group located along a second edge of the plurality of banks opposite the first pad group, and a pad control section configured to provide first and second bonding signals and to implement control operation in response to a test mode signal and a bonding option signal to selectively employ signals from the first and second pad groups.

Abstract: The present invention relates to a subscriber station security-related parameter negotiation method in a wireless portable Internet system. The subscriber station security-related parameter negotiation method includes security-related parameters in transmitting/receiving basic capability negotiation request messages and basic capability negotiation response messages such that the subscriber station and the base station negotiate the subscriber station security-related parameters. The security-related parameters include an authorization policy support subfield used to negotiate an authorization policy between the subscriber station and the base station, and message authentication code mode subfields used to negotiate a message authentication code mode.

Abstract: A semiconductor apparatus includes: a plurality of electrical fuses; a rupture unit configured to rupture an electrical fuse in response to rupture information applicable to the plurality of electrical fuses, when a rupture enable signal is activated; a scan unit configured to output information on whether an each of the plurality of electrical fuses are ruptured or not, as scan information, when a scan enable signal is activated; and a shift register unit configured to receive an input signal in synchronization with a clock signal and store the input signal as the rupture information, and configured to receive the scan information and output the scan information as an output signal in synchronization with the clock signal.

Abstract: A test circuit of a semiconductor integrated circuit includes a through via, a voltage driving unit, and a determination unit. The through via receives an input voltage. The voltage driving unit is connected to the through via to receive the input voltage, changes a level of the input voltage in response to a test control signal, and generates a test voltage. The determination unit compares the input voltage with the test voltage to outputs a resultant signal.

Abstract: An operation method of a memory system including a memory and a memory controller includes transmitting defective-cell address information to the memory controller from the memory at an initial operation of the memory, wherein the defective-cell address information includes an address of a defective cell of the memory, and accessing, by the memory controller, an area of the memory excluding an area indicated by the defective-cell address information inside the memory.