Abstract: A semiconductor device with EMI shield and a fabricating method thereof are provided. In one embodiment, the semiconductor device includes EMI shield on all six surfaces of the semiconductor device without the use of a discrete EMI lid.

Abstract: A semiconductor device includes a first internal circuit coupled to first and second voltage terminals for receiving first and second voltages; a second internal circuit coupled to the first and second voltage terminals for receiving the first and second voltages; a first power gating circuit coupled between at least one of the first and second voltage terminals and the first internal circuit, the first power gating circuit being suitable for disconnecting at least one of the first and second voltages based on a first mode signal in a first mode; a second power gating circuit coupled between at least one of the first and second voltage terminals and the second internal circuit, the second power gating circuit being suitable for disconnecting at least one of the first and second voltages based on an integrated mode signal in the first mode and a second mode; and a control circuit suitable for generating the first mode signal and the integrated mode signal.

Abstract: A semiconductor device may include: a holding control circuit suitable for generating a holding control signal and an option setting information signal, based on a first command signal; a holding circuit suitable for generating a held option setting information signal based on the holding control signal and the option setting information signal; an operation control circuit suitable for generating an operation mode signal based on a second command signal; a setting control circuit suitable for generating a setting control signal based on the operation mode signal and the held operation setting information signal; and a memory region suitable for performing an operation based on the setting control signal and the operation mode signal.

Abstract: A semiconductor device includes a column operation control circuit and a bank column address generation circuit. The column operation control circuit generates first and second bank address control signals as well as first and second bank control pulses from first and second bank selection signals in response to a synthesis control pulse such that data in a first bank and data in a second bank are simultaneously outputted in a first mode. The bank column address generation circuit generates first and second bank column addresses for selecting the first and second banks from a column address in response to the first and second bank address control signals.

Abstract: A semiconductor device includes a bank group selection signal generation circuit and a bank group address generation circuit. The bank group selection signal generation circuit stores a bank address based on a command pulse generated to perform a read operation or a write operation. The bank group selection signal generation circuit outputs the stored bank address as a bank group selection signal. The bank group address generation circuit generates a bank group address and an internal bank group address for performing a column operation of a cell array included in a bank group selected based on the bank group selection signal.

Abstract: A power gating circuit is provided. The power gating circuit includes a logic gate group. The power gating circuit also includes a first switching circuit coupled to first and second supply voltages and the logic gate group. The power gating circuit further includes a second switching circuit coupled to the first and second supply voltages and the logic gate group. The first and second supply voltages are supplied to the logic gate group through the first switching circuit based on a voltage select signal. The first and second supply voltages are supplied to the logic gate group through the second switching circuit based on the voltage select signal and a power down signal.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising one or more conductive shielding members and an EMI shielding layer, and a method of manufacturing thereof.

Abstract: A semiconductor device includes: a memory region selection circuit for generating memory region select signals based on a memory region address signal and a mode identification signal, and activating one or more memory region select signals among memory region select signals during a first mode, or activating two or more memory region select signals among the memory region select signals during a second mode; a column selection circuit for generating column select signals based on a column address signal and the mode identification signal, and changing the column select signals during the first mode, or retaining the column select signals during the second mode; and memory regions of which one or more memory regions are accessed during the first mode or two or more memory regions are accessed during the second mode, based on the memory region select signals and the column select signals.

Abstract: A power gating control circuit may include a transmission control circuit configured to receive a first fuse signal and output a second fuse signal based on a level of the first fuse signal in a normal mode or output a second fuse signal regardless of a level of the first fuse signal in a power down mode. The power gating control circuit may include a logic circuit block including logic gates and configured to apply the second fuse signal to the logic gates.

Abstract: A semiconductor device may include: a holding control circuit suitable for generating a holding control signal and an option setting information signal, based on a first command signal; a holding circuit suitable for generating a held option setting information signal based on the holding control signal and the option setting information signal; an operation control circuit suitable for generating an operation mode signal based on a second command signal; a setting control circuit suitable for generating a setting control signal based on the operation mode signal and the held operation setting information signal; and a memory region suitable for performing an operation based on the setting control signal and the operation mode signal.

Abstract: A power gating control circuit may include a transmission control circuit configured to receive a first fuse signal and output a second fuse signal based on a level of the first fuse signal in a normal mode or output a second fuse signal regardless of a level of the first fuse signal in a power down mode. The power gating control circuit may include a logic circuit block including logic gates and configured to apply the second fuse signal to the logic gates.

Abstract: An air cleaner includes a first air cleaner having an output part, a second air cleaner configured to be electrically connectable to the first air cleaner, a power adapter detachably provided to supply power to the second air cleaner, a first input terminal provided in the second air cleaner and configured to be electrically connected to the output part, a second input terminal provided in the second air cleaner and configured to be electrically connected to the power adapter; and a switch configured to electrically connect the first input terminal to the output part or to electrically connect the second input terminal to the power adapter.

Abstract: Disclosed herein is an air cleaner capable of being coupled or separated in a vertical direction to improve space utilization. An air cleaner may include a first air cleaning module provided with a first connection unit, and a second air cleaning module detachably coupled to the first air cleaning module and provided with a second connection unit, wherein the second connection unit is configured to be detachably coupled to the first connection unit, and configured to be rotatable with respect to the first connection unit when the second connection unit is coupled to the first connection unit.

Abstract: A semiconductor device includes a first internal circuit coupled to first and second voltage terminals for receiving first and second voltages; a second internal circuit coupled to the first and second voltage terminals for receiving the first and second voltages; a first power gating circuit coupled between at least one of the first and second voltage terminals and the first internal circuit, the first power gating circuit being suitable for disconnecting at least one of the first and second voltages based on a first mode signal in a first mode; a second power gating circuit coupled between at least one of the first and second voltage terminals and the second internal circuit, the second power gating circuit being suitable for disconnecting at least one of the first and second voltages based on an integrated mode signal in the first mode and a second mode; and a control circuit suitable for generating the first mode signal and the integrated mode signal.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a stackable semiconductor device with small size and fine pitch and a method of manufacturing thereof.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising one or more conductive shielding members and an EMI shielding layer, and a method of manufacturing thereof.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising one or more conductive shielding members and an EMI shielding layer, and a method of manufacturing thereof.

Abstract: A semiconductor device includes a monitoring circuit suitable for generating a monitoring signal indicating whether a speed of a memory clock signal is changed based on a speed information signal representing speed information of the memory clock signal; a cycle control circuit suitable for generating a refresh cycle control signal for controlling a refresh cycle based on a system clock signal, the memory clock signal, the monitoring signal and a refresh flag signal; and a control circuit suitable for generating the memory clock signal and the refresh flag signal based on the speed information signal, the system clock signal and the refresh cycle control signal.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising a semiconductor die coupled to a substrate and surrounded by a perforated metal plane and a method of manufacturing thereof.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising one or more conductive shielding members and an EMI shielding layer, and a method of manufacturing thereof.