Abstract: A pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.

Abstract: In a memory device having an N number of banks, a refresh operation according to a piled refresh scheme is performed during a self-refresh mode to refresh the N number of banks in regular sequence when it is necessary to refresh all of the N number of banks. A refresh operation according to a Partial Array Self Refresh (PASR) scheme is performed during a self-refresh mode when it is necessary to refresh only an i number of banks (where 1<i?N?1) from among the N number of banks. During an auto-refresh mode, a refresh operation according to the piled refresh scheme is performed.

Abstract: A partial array self refresh (PASR) control apparatus for use in a semiconductor memory device having a plurality of banks includes: a bank deselection unit having a plurality of bank deselection signal output units for receiving a plurality of PASR code signals, wherein input terminal lines of each bank deselection signal output unit and signal lines of the plurality of PASR code signals are crossed each other and are selectively coupled each other.

Abstract: Provided are a delay locked loop (DLL) and a method for generating a divided clock therein. In the DLL, a width of a reference frequency for phase comparison can be changed depending on a magnitude of an operating frequency. In the DLL, a clock buffer receives a clock equal to an external clock and generates an internal clock. An enable clock generator generates a 1-period enable clock or a 2-period enable clock using a command signal generated for performing a predefined operation. The command signal is generated according to an address command signal inputted from an exterior. A clock divider divides the internal clock to generate a divided clock. The divided clock is controlled by the 1-period enable clock or the 2-period enable clock, such that the divided clock is made to be a 1-period based dividing clock or a 2-period based dividing clock.

Abstract: In a memory device having an N number of banks, a refresh operation according to a piled refresh scheme is performed during a self-refresh mode to refresh the N number of banks in regular sequence when it is necessary to refresh all of the N number of banks. A refresh operation according to a Partial Array Self Refresh (PASR) scheme is performed during a self-refresh mode when it is necessary to refresh only an i number of banks (where 1<i?N-1) from among the N number of banks. During an auto-refresh mode, a refresh operation according to the piled refresh scheme is performed.

Abstract: Disclosed is a continuous process for the production of optically pure (S)-?-hydroxy-?-butyrolactone having constantly maintained optical activity, consisting of hydrogenating 2-50 wt % of a substituted carboxylic acid derivative in a solvent using a fixed bed reactor filled with a precious metal catalyst-impregnated inorganic oxide carrier at 50-500° C. under pressure of 15-5,500 psig at weight-space-velocity of 0.1-10 h?1, in which a molar ratio of hydrogen to carboxylic acid derivative ranges from 2 to 10. The desired material can be produced in higher optical purity and at higher yield by the current process which is relatively simpler and environmentally safer than conventional processes. Additionally, increased production efficiency leads to production of the desired material on a large scale.

Abstract: Disclosed is an optical pickup apparatus. Particularly, a photo detector for use in the optical pickup apparatus detects a beam reflected from the disc, and includes a substrate for transmitting three beams (one main beam and two sub beams) reflected from the optical disc; a liquid crystal for refracting the two sub beams, that are transmitted through the substrate, at different refractive indexes according to the wavelength of a laser beam outputted from the laser diode; an electrode material for supplying power to the liquid crystal; a switch for adjusting the magnitude of an applied voltage to the electrode material; and a photodiode on which the main beam and the refracted sub beams while transmitting the substrate and the liquid crystal are projected, and transformed into electric signals.

Abstract: A hinge apparatus includes a substantially cylindrical holder having at least one guide hole with a predetermined degree slope that extends in a longitudinal direction. A hinge shaft includes a substantially cylindrical surface configured to linearly move in the longitudinal direction of the holder. A guide pin has an end located inside the guide hole and is configured to extend through the cylindrical surface of the hinge shaft. Therefore, when the hinge shaft moves linearly in the holder, the guide pin moves along the guide hole so that the hinge shaft rotates in the holder.

Abstract: A partial array self refresh (PASR) control apparatus for use in a semiconductor memory device having a plurality of banks includes: a bank deselection unit having a plurality of bank deselection signal output units for receiving a plurality of PASR code signals, wherein input terminal lines of each bank deselection signal output unit and signal lines of the plurality of PASR code signals are crossed each other and are selectively coupled each other.

Abstract: A delay detecting apparatus detects delay amounts of delay elements in a semiconductor device by using a test mode. The semiconductor device comprises a delay signal detecting unit for detecting delays of delay elements in the semiconductor device by using a signal that is synchronized with an external clock, and a delay signal outputting unit for outputting a delayed signal from the delay signal detecting unit to a data pad by using the signal that is synchronized with the external clock.

Abstract: The present invention relates to a self-refresh apparatus and method. In the self-refresh method according to the present invention, when a partial array self-refresh operation is performed on a bank, internal address is counted in a predetermined cycle corresponding to a refresh rate regardless of PASR types. The bank is selectively activated depending on the PASR types. As a result, errors of the refresh rate which result from a half of bank or quarter of bank self refresh operation can be prevented.

Abstract: A portable communication device for games is disclosed. The portable communication device comprises a body housing having a display unit, a first key swing housing connected to the body housing such that the first key swing housing can be rotated about a first hinge axis while being opposite to the body housing for exposing/covering one side display section of the display unit, and a second key swing housing connected to the body housing such that the second key swing housing can be rotated about a second hinge axis while being opposite to the body housing for exposing/covering the other side display section of the display unit. The first and second key swing housings are rotatably connected to the body housing by means of a hinge apparatus.

Abstract: A memory device for adjusting a write recovery time includes a synchronous write recovery time controlling block which receives a control signal for performing an auto-precharge operation and delays out the control signal as long as a certain clock section of the operational clock corresponding to the write recovery time, an asynchronous write recovery time controlling block for delaying out the control signal coupled thereto as long as a fixed delay time corresponding to the write recovery time, a selecting block for choosing the synchronous write recovery time controlling block or the asynchronous write recovery time controlling block, and an auto-precharge controlling block which outputs as an auto-precharge execution signal used in performing the auto-precharge operation a signal outputted from the synchronous write recovery time controlling block or the asynchronous write recovery time controlling block in response to a write command.

Abstract: A portable communication device including a first housing and second housing, wherein the second housing is connected to the first housing so that it is rotatable around a first hinge axis while facing a top surface of the first housing to allow movement toward or away from the first housing. The device also includes a third housing connected to the second housing so that it is rotatable around the first hinge axis while facing the top surface of the first housing to allow movement toward or away from the first housing, and rotatable around a third hinge axis to allow rotational movement of a display. A battery pack, serving as a grip, is connected to the first housing so that it is rotatable around a third hinge axis while facing a bottom surface of the first housing to allow movement toward or away from the first housing. A sensing unit is provided to sense whether the battery pack is rotated.

Abstract: Disclosed is a method for testing a memory device with a long-term clock signal by automatically performing precharge only after activation. In this method, a signal for precharging the banks of the memory device is automatically generated only at the falling edge of an external signal when a signal for activating the banks is applied. Accordingly, the present invention ensures a stable test of the memory device, reducing the testing time.

Abstract: The present invention relates to a self-refresh apparatus and method. In the self-refresh method according to the present invention, when a partial array self-refresh operation is performed on a bank, internal address is counted in a predetermined cycle corresponding to a refresh rate regardless of PASR types. The bank is selectively activated depending on the PASR types. As a result, errors of the refresh rate which result from a half of bank or quarter of bank self refresh operation can be prevented.

Abstract: A semiconductor memory device that generates, during a test operation, a burst control signal having a short pulse in a disable time of a burst control signal by using a pulse generator to control a precharge time. Accordingly, the semiconductor memory device, when receiving a high frequency operation clock signal, can be tested without delay of a test time by using a test circuit operated synchronously with a low frequency operation clock signal.

Abstract: An internal voltage generating apparatus for a semiconductor memory device is described herein. The internal voltage generating apparatus is configured to execute an internal voltage margin test with a small number of pads by installing a forcing pad and fuse (or switch) in an initial reference voltage generating terminal during a multi-chip product test of the DRAM to cut down expenses, and to overcome load or noise due to the forcing pad by cutting (switching off) the fuse after a wafer level test during a normal operation.

Abstract: The present invention generally relates to a self-refresh device and method, and more specifically, to a PASR (Partial Array Self-Refresh) device and method for selectively performing a refresh operation on a cell array requiring a refresh in a self-refresh mode. According to the present invention, a selective refresh operation is performed on a cell array requiring a refresh by setting the self-refresh information as an EMRS (Extended Mode Register Set) code and selectively activating a cell array in response to a bank selection address. Here, a refresh operation is not performed on a cell array which does not require a refresh in a self-refresh mode. Accordingly, the power consumption of a memory can be considerably reduced, and noise can be also decreased by reducing peak operation current.

Abstract: An internal voltage generating apparatus for a semiconductor memory device is described herein. The internal voltage generating apparatus is configured to execute an internal voltage margin test with a small number of pads by installing a forcing pad and fuse (or switch) in an initial reference voltage generating terminal during a multi-chip product test of the DRAM to cut down expenses, and to overcome load or noise due to the forcing pad by cutting (switching off) the fuse after a wafer level test during a normal operation.