Abstract: A method of manufacturing a wiring board including an insulating layer where a semiconductor chip is embedded includes: forming, on a supporting board, the insulating layer where the semiconductor chip is embedded and a wiring connected to the semiconductor chip; removing the supporting board by etching; and simultaneously forming first and second reinforcing layers so as to sandwich the insulating layer after removing the supporting board.

Abstract: A semiconductor wafer is thinned to a predetermined thickness by grinding the backside thereof (which is opposite to the side where a plurality of devices are formed and metal posts are further formed), and then a metal layer made of metal having a linear thermal expansion coefficient close to that of the semiconductor wafer is formed on the ground side. Further, the semiconductor wafer is sealed with resin, metal bumps are bonded to the tops of the metal posts (barrier metal layer), and then the semiconductor wafer is divided into the respective semiconductor devices. Silicon is used as material for the semiconductor wafer, and tungsten or molybdenum is used as metal constituting the metal layer.

Abstract: In an electronic parts packaging structure of the present invention constructed by stacking a plurality of sheet-like units in a thickness direction, each of the units includes a first insulating layer, wirings formed on one surface of the first insulating layer, a semiconductor chip (electronic parts) connected to the wirings, a second insulating layer formed on an one surface side of the first insulating layer to cover the semiconductor chip, and connecting portions (terminals and contact vias) for connecting electrically the wirings and wirings of other unit, wherein arrangement of the first insulating layer, the semiconductor chip, the wirings, and the second insulating layer is symmetrical between units adjacent in a thickness direction.

Abstract: A laminated semiconductor package includes: a first package having: an insulating layer; a first semiconductor chip embedded in the insulating layer; a wiring connected to the first semiconductor chip; a first connecting section which is formed on a first face side of the insulating layer and connected to the wiring; and a second connecting section which is formed on a second face side of the insulating layer and connected to the wiring, the second face side being opposite to the first face side; and a second package having: a second semiconductor chip; and a third connecting section connected to the second semiconductor chip. In the laminated semiconductor chip, the first package and the second package are laminated one on the other, and the second connecting section and the third connecting section are connected to each other.

Abstract: A wiring board includes: a semiconductor chip; an insulating layer in which the semiconductor chip is embedded; a wiring connected to the semiconductor chip; and reinforcing layers for reinforcing the insulating layer, the reinforcing layers respectively formed on a front face side of the insulating layer and a rear face side of the insulating layer.

Abstract: A method for forming a through electrode is disclosed. The through electrode integrally comprises a columnar electrode filling a through hole, a lower end electrode pad formed on a lower end side of a columnar electrode and having an area wider than the cross section of the through hole, and an upper end electrode pad formed on an upper end side of the columnar electrode and having an area wider than the cross section of the through hole. The lower end electrode pad is arranged is arranged to occlude a lower end opening of the through hole. The columnar electrode fills the through hole by laminating copper on the lower end electrode pad.

Abstract: A method of manufacturing a wiring board includes: forming a first insulating layer on a supporting board; mounting at least one reinforcing member on the first insulating layer; mounting at least one semiconductor chip on the first insulating layer; forming a second insulating layer on the reinforcing member and the semiconductor chip; and forming a wiring on the second insulating layer, the wiring being connected to the semiconductor chip.

Abstract: A wiring board includes an insulating layer in which a semiconductor chip is embedded, and a wiring structure connected to the semiconductor chip. A reinforcing member reinforcing the insulating layer is embedded in the insulating layer. This enables reduction in a thickness of the wiring board and a suppression of warpage of the wiring board.

Abstract: A method of manufacturing a semiconductor device having a build-up layer for wiring between semiconductor elements and external connection terminals is disclosed. The method comprises steps of forming a rewiring layer on a wafer, placing the wafer on a stretchable dicing tape, dicing the wafer placed on the dicing tape, forming a clearance between adjacent semiconductor elements by stretching the dicing tape, forming a semiconductor device continuous body by forming a build-up layer on the semiconductor elements and the clearance, and forming semiconductor devices by dicing the semiconductor device continuous body.

Abstract: A method of manufacturing a semiconductor device is disclosed. The method comprises a first step of grinding a second principle surface of a semiconductor substrate opposite to a first principle surface of the semiconductor substrate on which semiconductor device elements are formed, a second step of attaching a support structure configured to support the semiconductor substrate to the second principle surface after the first step, and a third step of detaching the semiconductor substrate from the support structure.

Abstract: A manufacturing method of a chip integrated substrate is disclosed. The manufacturing method includes a first step that forms a wiring structure to be connected to a semiconductor chip on a first core substrate; a second step that disposes the semiconductor chip on a second core substrate; and a third step that bonds the first core substrate on which the wiring structure is formed to the second core substrate on which the semiconductor chip is disposed. In addition, the manufacturing method includes a step that removes the first core substrate after the third step and a step that removes the second core substrate after the third step.

Abstract: A disclosed substrate is composed of a base member having a through-hole, a penetrating via provided in the through-hole, and a wiring connected to the penetrating via. The penetrating via includes a penetrating part having two ends on both sides of the base member, which is provided in the through-hole, a first protrusion protruding from the base member, which is formed on a first end of the penetrating part so as to be connected to the wiring, and a second protrusion protruding from the base member, which is formed on a second end of the penetrating part. The first protrusion and second protrusion are wider than a diameter of the through-hole.

Abstract: A disclosed substrate includes a base member having a through-hole, and a conductive metal filling in the through-hole so as to form a penetrating via. The penetrating via contains a conductive core member that is substantially at the central axis of the through-hole.

Abstract: A disclosed substrate having a built-in semiconductor chip includes the built-in semiconductor chip, a resin member having the built-in semiconductor chip contained therein and external connection terminals. The resin member contains a resin and 60 to 90% by weight of spherical filler.

Abstract: Insulating films (13, 14) are formed on the surface of a semiconductor wafer (30) on the side on which a plurality of devices are formed. Then, conductor layers (15, 16) are formed to cover opening portions from which electrode pads (12) of each device are exposed. Furthermore, a resist layer (R2) is formed to have opening portions from which terminal formation portions of the conductor layer are exposed, and metal posts (17) are formed on the terminal formation portions of the conductor layer (16) using the resist layer (R2) as a mask. Then, thinning of the semiconductor wafer (30) is performed to a predetermined thickness by grinding the back surface thereof. Thereafter, the resist layer (R2) is removed; an unnecessary portion (15) of the conductor layer is further removed; sealing with sealing resin is performed with the top portions of the metal posts (17) being exposed; metal bumps are bonded to the top portions of the metal posts (17); and the semiconductor wafer is divided into each device.

Abstract: A method for forming a through electrode is disclosed. The through electrode integrally comprises a columnar electrode filling a through hole, a lower end electrode pad formed on a lower end side of a columnar electrode and having an area wider than the cross section of the through hole, and an upper end electrode pad formed on an upper end side of the columnar electrode and having an area wider than the cross section of the through hole. The lower end electrode pad is arranged is arranged to occlude a lower end opening of the through hole. The columnar electrode fills the through hole by laminating copper on the lower end electrode pad.

Abstract: A method of fabricating a built-in chip type substrate containing a semiconductor chip is disclosed. The method comprises a first step of mounting the semiconductor chip on a substrate; a second step of forming chip connection wiring connected to the semiconductor chip mounted on the substrate; and a step of forming an alignment post on the substrate before the first step, the alignment post being used for positioning the chip connection wiring.

Abstract: A method of manufacturing a semiconductor device is disclosed. The method comprises a first step of grinding a second principle surface of a semiconductor substrate opposite to a first principle surface of the semiconductor substrate on which semiconductor device elements are formed, a second step of attaching a support structure configured to support the semiconductor substrate to the second principle surface after the first step, and a third step of detaching the semiconductor substrate from the support structure.

Abstract: A method of manufacturing a semiconductor device having a build-up layer for wiring between semiconductor elements and external connection terminals is disclosed. The method comprises steps of forming a rewiring layer on a wafer, placing the wafer on a stretchable dicing tape, dicing the wafer placed on the dicing tape, forming a clearance between adjacent semiconductor elements by stretching the dicing tape, forming a semiconductor device continuous body by forming a build-up layer on the semiconductor elements and the clearance, and forming semiconductor devices by dicing the semiconductor device continuous body.

Abstract: A method of forming an electrode on a semiconductor wafer by plating is disclosed that is able to reliably prevent leakage of a plating solution during the plating process. The plating method comprises the steps of forming a conductive layer on a semiconductor wafer; forming a negative resist layer on the conductive layer; exposing a center portion of the negative resist layer; exposing a peripheral region of the negative resist layer after the step of exposing the center portion of the negative resist layer; developing the exposed negative resist layer to form a predetermined plating pattern; and performing plating on the plating pattern.