Patents by Inventor Takaharu Yamano

Takaharu Yamano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050112800
    Abstract: A semiconductor wafer is thinned to a predetermined thickness by grinding the backside thereof (which is opposite to the side where a plurality of devices are formed and metal posts are further formed), and then a metal layer made of metal having a linear thermal expansion coefficient close to that of the semiconductor wafer is formed on the ground side. Further, the semiconductor wafer is sealed with resin, metal bumps are bonded to the tops of the metal posts (barrier metal layer), and then the semiconductor wafer is divided into the respective semiconductor devices. Silicon is used as material for the semiconductor wafer, and tungsten or molybdenum is used as metal constituting the metal layer.
    Type: Application
    Filed: November 16, 2004
    Publication date: May 26, 2005
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Takaharu Yamano
  • Publication number: 20040253802
    Abstract: A method of forming a plating electrode is disclosed that provides an increased degree of freedom in shape and position of the plating electrode. A light shielding layer is formed on a negative resist layer in a ring shape corresponding to the edge of the negative resist layer. Then, with a projection lithography stepper, and only one type of reticle pattern, specified regions of the negative resist layer are exposed one by one. Subsequently, the portion of the negative resist layer below the light shielding layer is removed by a developing treatment, and the portion of a conductive metal layer previously covered by the removed negative resist layer 120 is exposed. This exposed portion of the conductive metal is used as the plating electrode.
    Type: Application
    Filed: June 1, 2004
    Publication date: December 16, 2004
    Inventor: Takaharu Yamano
  • Publication number: 20040207082
    Abstract: A plurality of semiconductor packages is collectively fabricated on a wafer in a batch process and the wafer is then diced to obtain discrete semiconductor packages. The semiconductor package is a stacked body formed by bonding two or more semiconductor devices. Each semiconductor device comprises a substrate and a device pattern formed on a surface of the substrate. The semiconductor devices are stacked in such a fashion that a device pattern surface of the lower semiconductor device faces a non-device pattern surface of the semiconductor device stacked on the same.
    Type: Application
    Filed: April 12, 2004
    Publication date: October 21, 2004
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takaharu Yamano, Takako Yoshihara, Masahiro Sunohara
  • Publication number: 20030094686
    Abstract: A semiconductor device comprises a semiconductor element having an electrode forming surface on which an electrode terminal is formed, an insulating layer made of phenol resin covering the electrode forming surface, and a rewiring pattern connected at one thereof to the electrode terminal and at the other end thereof to an external connecting terminal. During a process for manufacturing the phenol resin is cured at a temperature of 180° C. to 200° C. to form the insulating layer.
    Type: Application
    Filed: November 13, 2002
    Publication date: May 22, 2003
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takahiro Iijima, Akihito Takano, Takaharu Yamano, Takako Yoshihara, Yoshikatsu Seki