Patents by Inventor Takahiro Arakida
Takahiro Arakida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120009704Abstract: A vertical cavity surface emitting laser capable of reducing parasitic capacitance while suppressing power consumption, and a method of manufacturing thereof are provided. The vertical cavity surface emitting laser includes a columnar mesa including, on a substrate, a first multilayer reflector, an active layer, and a second multilayer reflector in order from the substrate side, and also including a current narrowing layer. The columnar portion of the mesa including the active layer and the current narrowing layer is formed within a region opposed to the first multilayer reflector and a region opposed to the second multilayer reflector, and a cross section area of the columnar portion is smaller than a cross section area of the second multilayer reflector.Type: ApplicationFiled: September 19, 2011Publication date: January 12, 2012Applicant: Sony CorporationInventors: Yuji Masui, Takahiro Arakida, Terukazu Naruse, Rintaro Koda, Naoki Jogan
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Patent number: 8085827Abstract: A Vertical Cavity Surface Emitting Laser capable of decreasing the lowering of the yield due to displacement and separation of a pedestal without enormous increase of the threshold value and more difficult manufacturing process is provided. A base of a mesa spreads over the top face of a lower DBR layer. The base is a non-flat face in which end faces of a plurality of layers are exposed. The non-flat face is generated due to etching unevenness in forming the mesa, and is in a state of a step in which end faces of a low-refractive index layer and a high-refractive index layer included in the lower DBR layer are alternatively exposed. At least one of the layers exposed in the non-flat face in the plurality of low-refractive index layers included in the lower DBR layer is an oxidation inhibition layer.Type: GrantFiled: March 3, 2009Date of Patent: December 27, 2011Assignee: Sony CorporationInventors: Tomoyuki Oki, Rintaro Koda, Naoki Jogan, Yuji Masui, Takahiro Arakida
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Patent number: 8077752Abstract: A Vertical Cavity Surface Emitting Laser (VCSEL) capable of providing high output of fundamental transverse mode while preventing oscillation of high-order transverse mode is provided. The VCSEL includes a semiconductor layer including an active layer and a current confinement layer, and a transverse mode adjustment section formed on the semiconductor layer. The current confinement layer has a current injection region and a current confinement region. The transverse mode adjustment section has a high reflectance area and a low reflectance area. The high reflectance area is formed in a region including a first opposed region opposing to a center point of the current injection region. A center point of the high reflectance area is arranged in a region different from the first opposed region. The low reflectance area is formed in a region where the high reflectance area is not formed, in an opposed region opposing to the current injection region.Type: GrantFiled: December 29, 2008Date of Patent: December 13, 2011Assignee: Sony CorporationInventors: Osamu Maeda, Masaki Shiozaki, Takahiro Arakida
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Publication number: 20110294236Abstract: A method of manufacturing a semiconductor device capable of largely increasing the yield and a semiconductor device manufactured by using the method is provided. After a semiconductor layer is formed on a substrate, as one group, a plurality of functional portions with at least one parameter value different from each other is formed in the semiconductor layer for every unit chip area. Then, a subject that is changed depending on the parameter value is measured and evaluated and after that, the substrate is divided for every chip area so that a functional portion corresponding with a given criterion as a result of the evaluation is not broken. Thereby, at least one functional portion corresponding with a given criterion can be formed by every chip area by appropriately adjusting each parameter value.Type: ApplicationFiled: August 8, 2011Publication date: December 1, 2011Applicant: Sony CorporationInventors: Yuji Masui, Takahiro Arakida, Yoshinori Yamauchi, Kayoko Kikuchi, Rintaro Koda, Norihiko Yamaguchi
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Patent number: 8040934Abstract: A vertical cavity surface emitting laser capable of reducing parasitic capacitance while suppressing power consumption, and a method of manufacturing thereof are provided. The vertical cavity surface emitting laser includes a columnar mesa including, on a substrate, a first multilayer reflector, an active layer, and a second multilayer reflector in order from the substrate side, and also including a current narrowing layer. The columnar portion of the mesa including the active layer and the current narrowing layer is formed within a region opposed to the first multilayer reflector and a region opposed to the second multilayer reflector, and a cross section area of the columnar portion is smaller than a cross section area of the second multilayer reflector.Type: GrantFiled: January 20, 2010Date of Patent: October 18, 2011Assignee: Sony CorporationInventors: Yuji Masui, Takahiro Arakida, Terukazu Naruse, Rintaro Koda, Naoki Jogan
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Publication number: 20110249696Abstract: There is provided a laser diode capable of setting a mesa diameter small without use of a method which loses reliability of a device, and is not easily controlled. The laser diode includes: a columnar mesa including a first multilayer film reflecting mirror, an active layer, and a second multilayer film reflecting mirror in this order, including an oxide confined layer having an unoxidized region in middle of a plane, and having a cross-sectional shape in a plane direction different from a cross-sectional shape of the unoxidized region in a plane direction; and a plurality of metal electrodes formed in regions on a top face of the mesa not facing the unoxidized region.Type: ApplicationFiled: March 30, 2011Publication date: October 13, 2011Applicant: Sony CorporationInventors: Yuji Masui, Takahiro Arakida, Kayoko Kikuchi, Terukazu Naruse, Koichi Kondo, Naoki Jogan
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Patent number: 8035187Abstract: The present invention provides a semiconductor light receiving element capable of reducing capacity while minimizing increase in travel time of carriers. The semiconductor light receiving element includes a semiconductor stacked structure including a first conductivity type layer, a light absorbing layer, and a second conductivity type layer having a light incidence plane in order. The semiconductor light receiving element has an oxidation layer including a non-oxidation region and an oxidation region in a stacking in-plane direction in the light absorbing layer or between the first conductivity type layer and the light absorbing layer.Type: GrantFiled: January 29, 2009Date of Patent: October 11, 2011Assignee: Sony CorporationInventors: Yoshinori Yamauchi, Takahiro Arakida, Rintaro Koda, Norihiko Yamaguchi, Yuji Masui, Tomoyuki Oki
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Publication number: 20110243174Abstract: There is provided a semiconductor light-emitting device including a temperature detecting section which is allowed to accurately estimate an element temperature. The semiconductor light-emitting device includes: one or a plurality of surface-emitting semiconductor light-emitting sections and one or a plurality of semiconductor temperature detecting sections on a semiconductor substrate, the surface-emitting semiconductor light-emitting sections emitting light in a direction normal to the semiconductor substrate, the semiconductor temperature detecting sections not emitting light to outside. The semiconductor light-emitting sections and the semiconductor temperature detecting sections have a PN junction or a PIN junction in a direction normal to the semiconductor substrate.Type: ApplicationFiled: March 24, 2011Publication date: October 6, 2011Applicant: Sony CorporationInventors: Osamu Maeda, Masaki Shiozaki, Susumu Sato, Takahiro Arakida, Shiro Uchida
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Publication number: 20110241571Abstract: A drive circuit and a drive current correcting method are described herein. The drive circuit comprises a current source that outputs a drive current, and a correction circuit that outputs a correction current. The correction circuit includes a first RC time constant circuit. An output terminal of the current source is connected to an output terminal of the correction circuit.Type: ApplicationFiled: February 8, 2011Publication date: October 6, 2011Applicant: Sony CorporationInventors: Osamu Maeda, Takeshi Yuwaki, Katsuhisa Daio, Koichi Kobe, Hirofumi Nakano, Takahiro Arakida
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Patent number: 8027370Abstract: The present invention provides a semiconductor device realizing improved adhesion between a low-dielectric-constant material and a semiconductor material. The semiconductor device includes, on a semiconductor layer, an adhesion layer and a low-dielectric-constant material layer in order from the semiconductor layer side. The adhesion layer has a projection/recess structure, and the low-dielectric-constant material layer is formed so as to bury gaps in the projection/recess structure.Type: GrantFiled: January 20, 2010Date of Patent: September 27, 2011Assignee: Sony CorporationInventors: Yuji Masui, Takahiro Arakida, Kayoko Kikuchi, Terukazu Naruse, Tomoyuki Oki, Naoki Jogan
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Patent number: 8022424Abstract: A method of manufacturing a semiconductor device capable of largely increasing the yield and a semiconductor device manufactured by using the method is provided. After a semiconductor layer is formed on a substrate, as one group, a plurality of functional portions with at least one parameter value different from each other is formed in the semiconductor layer for every unit chip area. Then, a subject that is changed depending on the parameter value is measured and evaluated and after that, the substrate is divided for every chip area so that a functional portion corresponding with a given criterion as a result of the evaluation is not broken. Thereby, at least one functional portion corresponding with a given criterion can be formed by every chip area by appropriately adjusting each parameter value.Type: GrantFiled: June 5, 2007Date of Patent: September 20, 2011Assignee: Sony CorporationInventors: Yuji Masui, Takahiro Arakida, Yoshinori Yamauchi, Kayoko Kikuchi, Rintaro Koda, Norihiko Yamaguchi
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Publication number: 20110194579Abstract: A Vertical Cavity Surface Emitting Laser (VCSEL) capable of providing high output of fundamental transverse mode while preventing oscillation of high-order transverse mode is provided. The VCSEL includes a semiconductor layer including an active layer and a current confinement layer, and a transverse mode adjustment section formed on the semiconductor layer. The current confinement layer has a current injection region and a current confinement region. The transverse mode adjustment section has a high reflectance area and a low reflectance area. The high reflectance area is formed in a region including a first opposed region opposing to a center point of the current injection region. A center point of the high reflectance area is arranged in a region different from the first opposed region. The low reflectance area is formed in a region where the high reflectance area is not formed, in an opposed region opposing to the current injection region.Type: ApplicationFiled: April 15, 2011Publication date: August 11, 2011Applicant: Sony CorporationInventors: Osamu Maeda, Masaki Shiozaki, Takahiro Arakida
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Publication number: 20110182315Abstract: A manufacturing method of a surface-emitting semiconductor laser includes the steps of: forming a stacked structure having a lower-multilayer film reflector including a lower oxidizable layer having at least one layer, an active layer having a light emitting region, an upper-multilayer film reflector including an upper oxidizable layer and an upper layer on a substrate in this order; providing a first groove in the upper layer; and providing a second groove including a portion overlapping the first groove in a planar shape and a portion not overlapping the first groove in the stacked structure.Type: ApplicationFiled: December 17, 2010Publication date: July 28, 2011Applicant: Sony CorporationInventors: Masaki Shiozaki, Osamu Maeda, Takahiro Arakida, Susumu Sato
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Publication number: 20110176570Abstract: A semiconductor light emitting device includes a first-conductivity-type first multilayer film reflecting mirror, and a second-conductivity-type second multilayer film reflecting mirror; a cavity layer; and a first conductive section, a second conductive section, and a third conductive section. The cavity layer has a stacked configuration including a first-conductivity-type or undoped first cladding layer, an undoped first active layer, a second-conductivity-type or undoped second cladding layer, a second-conductivity-type first contact layer, a first-conductivity-type second contact layer, a first-conductivity-type or undoped third cladding layer, an undoped second active layer, and a second-conductivity-type or undoped fourth cladding layer.Type: ApplicationFiled: March 21, 2011Publication date: July 21, 2011Applicant: Sony CorporationInventors: Yuji Masui, Takahiro Arakida, Yoshinori Yamauchi, Rintaro Koda, Tomoyuki Oki, Naoki Jogan
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Publication number: 20110164646Abstract: A method of manufacturing a laser diode array capable of inhibiting electric cross talk is provided. The method of manufacturing a laser diode array includes a processing step of forming a peel layer containing an oxidizable material and a vertical resonator structure over a first substrate sequentially from the first substrate side by crystal growth, and then selectively etching the peel layer and the vertical resonator structure to the first substrate, thereby processing into a columnar shape, a peeling step of oxidizing the peel layer from a side face, and then peeling the vertical resonator structure of columnar shape from the first substrate, and a rearrangement step of jointing a plurality of vertical resonator structures of columnar shape obtained by the peeling step to a surface of a metal layer of a second substrate formed with the metal layer on the surface.Type: ApplicationFiled: March 11, 2011Publication date: July 7, 2011Applicant: Sony CorporationInventors: Osamu Maeda, Masaki Shiozaki, Takahiro Arakida
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Patent number: 7965750Abstract: A semiconductor light emitting device includes a first-conductivity-type first multilayer film reflecting mirror, and a second-conductivity-type second multilayer film reflecting mirror; a cavity layer; and a first conductive section, a second conductive section, and a third conductive section. The cavity layer has a stacked configuration including a first-conductivity-type or undoped first cladding layer, an undoped first active layer, a second-conductivity-type or undoped second cladding layer, a second-conductivity-type first contact layer, a first-conductivity-type second contact layer, a first-conductivity-type or undoped third cladding layer, an undoped second active layer, and a second-conductivity-type or undoped fourth cladding layer.Type: GrantFiled: April 21, 2009Date of Patent: June 21, 2011Assignee: Sony CorporationInventors: Yuji Masui, Takahiro Arakida, Yoshinori Yamauchi, Rintaro Koda, Tomoyuki Oki, Naoki Jogan
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Patent number: 7960195Abstract: A method of manufacturing a laser diode array capable of inhibiting electric cross talk is provided. The method of manufacturing a laser diode array includes a processing step of forming a peel layer containing an oxidizable material and a vertical resonator structure over a first substrate sequentially from the first substrate side by crystal growth, and then selectively etching the peel layer and the vertical resonator structure to the first substrate, thereby processing into a columnar shape, a peeling step of oxidizing the peel layer from a side face, and then peeling the vertical resonator structure of columnar shape from the first substrate, and a rearrangement step of jointing a plurality of vertical resonator structures of columnar shape obtained by the peeling step to a surface of a metal layer of a second substrate formed with the metal layer on the surface.Type: GrantFiled: July 23, 2008Date of Patent: June 14, 2011Assignee: Sony CorporationInventors: Osamu Maeda, Masaki Shiozaki, Takahiro Arakida
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Publication number: 20110122910Abstract: The present invention provides a semiconductor device realizing reduced occurrence of a defect such as a crack at the time of adhering elements to each other. The semiconductor device includes a first element and a second element adhered to each other. At least one of the first and second elements has a pressure relaxation layer on the side facing the other of the first and second elements, and the pressure relaxation layer includes a semiconductor part having a projection/recess part including a projection projected toward the other element, and a resin part filled in a recess in the projection/recess part.Type: ApplicationFiled: January 31, 2011Publication date: May 26, 2011Applicant: Sony CorporationInventors: Rintaro Koda, Takahiro Arakida, Yuji Masui, Tomoyuki Oki
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Publication number: 20110096806Abstract: The present invention provides a semiconductor light emitting device realizing increased light detection precision by a simple manufacture process. One or more second oxidation layers are provided between an active layer and a semiconductor light detecting element in addition to a first oxidation layer for narrowing current. Since natural emission light includes many divergence components, the natural emission light is reflected and scattered by the second oxidation layer, and propagation of the natural emission light to the semiconductor light detecting element side is suppressed. The detection level of the natural emission light by the semiconductor light detecting element decreases, and light detection precision increases. The first and second oxidation layers are formed by a single oxidizing process so that the manufacturing process is simplified.Type: ApplicationFiled: September 30, 2010Publication date: April 28, 2011Applicant: Sony CorporationInventors: Takahiro Arakida, Shiro Uchida, Masaki Shiozaki, Osamu Maeda
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Publication number: 20110075691Abstract: A correction circuit is provided, which may reduce dullness of a light output waveform due to wavelength detuning. The correction circuit includes an RC time constant circuit. The RC time constant circuit is used to correct a waveform of a current pulse outputted from a current source, the current source driving a surface-emitting semiconductor laser in a pulsed manner, so that a pulse waveform of light output of the semiconductor laser is approximately a rectangle.Type: ApplicationFiled: August 23, 2010Publication date: March 31, 2011Applicant: Sony CorporationInventors: Osamu Maeda, Katsuhisa Daio, Koichi Kobe, Takehiro Taniguchi, Takahiro Arakida