Patents by Inventor Takahiro Irita

Takahiro Irita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11327830
    Abstract: A semiconductor device includes a master circuit which outputs a first write request signal for requesting to write data, a bus which receives the data and the first write request signal, a bus control unit which is arranged on the bus, generates an error detection code for the data and generates a second write request signal which includes second address information corresponding to first address information included in the first write request signal and memory controllers which each write the data into a storage area of an address designated by the first write request signal and writes the error detection code into a storage area of an address designated by the second write request signal in the storage areas of memories.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: May 10, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kimihiko Nakazawa, Takahiro Irita
  • Patent number: 11294835
    Abstract: A semiconductor device includes a first master and a second master configured to issue requests for accessing to a memory, a first request issuing controller coupled to the first master, and configured to hold the request issued from the first master, a second request issuing controller coupled to the second master, and configured to hold the request issued from the second master, a bus arbiter coupled to the first request issuing controller and the second request issuing controller, a memory controller coupled to the bus arbiter, and including a buffer configured to store the requests issued from the first master and the second master, and a central bus controller configured to grant access rights to the first request issuing controller and the second request issuing controller based on space information of the buffer.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: April 5, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Sho Yamanaka, Toshiyuki Hiraki, Yoshihiko Hotta, Takahiro Irita
  • Patent number: 11221789
    Abstract: When a plurality of write data is merged to generate a code for protecting data stored in the main memory, the write data is protected in the memory controller. A first code generation unit generates a first code based on the write data stored in a first sub memory, and stores the generated first code in a second sub memory. The sub memory controller reads the write data to be merged from the first sub memory, and verifies whether the read write data includes an error by using the first code stored in the second sub memory. When the read write data does not include an error, the sub memory controller merges valid data of the write data read from the first sub memory, and outputs the merged data to a second code generation unit. The second code generation unit generates a second code based on the merged data.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: January 11, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Sho Yamanaka, Nobuhiko Honda, Takahiro Irita
  • Publication number: 20210294691
    Abstract: In a data processing device comprising a memory controller controlling writing/reading of data to/from the memory, a processor requesting writing/reading of data, and an error detection module requesting writing/reading of data to/from the memory controller in accordance with a request from the processor, an error detection module calculates a first error detection code of the first data having a write request from the processor, reads the second data having a read request from the processor from the memory, calculates a second error detection code from the read data, compares the first error detection code and the second error detection code, and transmits the result of the comparison to the external module.
    Type: Application
    Filed: March 17, 2020
    Publication date: September 23, 2021
    Inventors: Katsushige MATSUBARA, Ryoji HASHIMOTO, Takahiro IRITA, Kenichi SHIMADA, Tetsuya SHIBAYAMA
  • Publication number: 20210141749
    Abstract: Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.
    Type: Application
    Filed: January 15, 2021
    Publication date: May 13, 2021
    Inventors: Katsuya MIZUMOTO, Toshiyuki HIRAKI, Nobuhiko HONDA, Sho YAMANAKA, Takahiro IRITA, Yoshihiko HOTTA
  • Publication number: 20210133020
    Abstract: A semiconductor device includes a master circuit which outputs a first write request signal for requesting to write data, a bus which receives the data and the first write request signal, a bus control unit which is arranged on the bus, generates an error detection code for the data and generates a second write request signal which includes second address information corresponding to first address information included in the first write request signal and memory controllers which each write the data into a storage area of an address designated by the first write request signal and writes the error detection code into a storage area of an address designated by the second write request signal in the storage areas of memories.
    Type: Application
    Filed: January 14, 2021
    Publication date: May 6, 2021
    Inventors: Kimihiko NAKAZAWA, Takahiro IRITA
  • Patent number: 10929317
    Abstract: Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: February 23, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsuya Mizumoto, Toshiyuki Hiraki, Nobuhiko Honda, Sho Yamanaka, Takahiro Irita, Yoshihiko Hotta
  • Patent number: 10922165
    Abstract: A semiconductor device includes a master circuit which outputs a first write request signal for requesting to write data, a bus which receives the data and the first write request signal, a bus control unit which is arranged on the bus, generates an error detection code for the data and generates a second write request signal which includes second address information corresponding to first address information included in the first write request signal and memory controllers which each write the data into a storage area of an address designated by the first write request signal and writes the error detection code into a storage area of an address designated by the second write request signal in the storage areas of memories.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: February 16, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kimihiko Nakazawa, Takahiro Irita
  • Publication number: 20210026788
    Abstract: A semiconductor device includes a first master and a second master configured to issue requests for accessing to a memory, a first request issuing controller coupled to the first master, and configured to hold the request issued from the first master, a second request issuing controller coupled to the second master, and configured to hold the request issued from the second master, a bus arbiter coupled to the first request issuing controller and the second request issuing controller, a memory controller coupled to the bus arbiter, and including a buffer configured to store the requests issued from the first master and the second master, and a central bus controller configured to grant access rights to the first request issuing controller and the second request issuing controller based on space information of the buffer.
    Type: Application
    Filed: October 9, 2020
    Publication date: January 28, 2021
    Inventors: Sho YAMANAKA, Toshiyuki HIRAKI, Yoshihiko HOTTA, Takahiro IRITA
  • Patent number: 10896919
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: January 19, 2021
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
  • Patent number: 10831683
    Abstract: A semiconductor device according to the present invention includes a plurality of masters (100), a memory controller (400a), a bus that connects the plurality of masters (100) and the memory controller (400a), a QoS information register (610) that stores QoS information of the plurality of masters (100), a right grant number controller (602) that calculates the number of grantable access rights based on space information of a buffer (401) of the memory controller (400a), a right grant selection controller (603a) that selects the master (100) which will be granted the access right based on the QoS information of the QoS information register (610) and the number of grantable rights from the right grant number controller (602), and a request issuing controller (201a) that does not pass a request of the master (100) which has not been granted the access right from the right grant selection controller (603a).
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: November 10, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Sho Yamanaka, Toshiyuki Hiraki, Yoshihiko Hotta, Takahiro Irita
  • Publication number: 20200201559
    Abstract: When a plurality of write data is merged to generate a code for protecting data stored in the main memory, the write data is protected in the memory controller. A first code generation unit generates a first code based on the write data stored in a first sub memory, and stores the generated first code in a second sub memory. The sub memory controller reads the write data to be merged from the first sub memory, and verifies whether the read write data includes an error by using the first code stored in the second sub memory. When the read write data does not include an error, the sub memory controller merges valid data of the write data read from the first sub memory, and outputs the merged data to a second code generation unit. The second code generation unit generates a second code based on the merged data.
    Type: Application
    Filed: November 15, 2019
    Publication date: June 25, 2020
    Inventors: Sho YAMANAKA, Nobuhiko HONDA, Takahiro IRITA
  • Publication number: 20200006384
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Application
    Filed: September 10, 2019
    Publication date: January 2, 2020
    Inventors: Yusuke KANNO, Hiroyuki MIZUNO, Yoshihiko YASU, Kenji HIROSE, Takahiro IRITA
  • Patent number: 10459646
    Abstract: Disclosed is a semiconductor device capable of performing compression and decompression with increased appropriateness. The semiconductor device includes a computing module and a memory control module. The computing module includes a computing unit and a compression circuit. The computing unit performs arithmetic processing. The compression circuit compresses data indicative of the result of arithmetic processing. The memory control module includes an access circuit and a decompression circuit. The access circuit writes compressed data into a memory and reads written data from the memory. The decompression circuit decompresses data read from the memory and outputs the decompressed data to the computing module.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: October 29, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsushige Matsubara, Seiji Mochizuki, Ryoji Hashimoto, Toshiyuki Kaya, Kimihiko Nakazawa, Takahiro Irita, Tetsuji Tsuda
  • Patent number: 10446581
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: October 15, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
  • Publication number: 20190163648
    Abstract: A semiconductor device includes a master circuit which outputs a first write request signal for requesting to write data, a bus which receives the data and the first write request signal, a bus control unit which is arranged on the bus, generates an error detection code for the data and generates a second write request signal which includes second address information corresponding to first address information included in the first write request signal and memory controllers which each write the data into a storage area of an address designated by the first write request signal and writes the error detection code into a storage area of an address designated by the second write request signal in the storage areas of memories.
    Type: Application
    Filed: September 13, 2018
    Publication date: May 30, 2019
    Inventors: Kimihiko NAKAZAWA, Takahiro IRITA
  • Publication number: 20190057052
    Abstract: A semiconductor device according to the present invention includes a plurality of masters (100), a memory controller (400a), a bus that connects the plurality of masters (100) and the memory controller (400a), a QoS information register (610) that stores QoS information of the plurality of masters (100), a right grant number controller (602) that calculates the number of grantable access rights based on space information of a buffer (401) of the memory controller (400a), a right grant selection controller (603a) that selects the master (100) which will be granted the access right based on the QoS information of the QoS information register (610) and the number of grantable rights from the right grant number controller (602), and a request issuing controller (201a) that does not pass a request of the master (100) which has not been granted the access right from the right grant selection controller (603a).
    Type: Application
    Filed: October 19, 2018
    Publication date: February 21, 2019
    Inventors: Sho YAMANAKA, Toshiyuki Hiraki, Yoshihiko Hotta, Takahiro Irita
  • Publication number: 20190004983
    Abstract: Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.
    Type: Application
    Filed: June 5, 2018
    Publication date: January 3, 2019
    Inventors: Katsuya Mizumoto, Toshiyuki Hiraki, Nobuhiko Honda, Sho Yamanaka, Takahiro Irita, Yoshihiko Hotta
  • Patent number: 10108562
    Abstract: A semiconductor device according to the present invention includes a plurality of masters (100), a memory controller (400a), a bus that connects the plurality of masters (100) and the memory controller (400a), a QoS information register (610) that stores QoS information of the plurality of masters (100), a right grant number controller (602) that calculates the number of grantable access rights based on space information of a buffer (401) of the memory controller (400a), a right grant selection controller (603a) that selects the master (100) which will be granted the access right based on the QoS information of the QoS information register (610) and the number of grantable rights from the right grant number controller (602), and a request issuing controller (201a) that does not pass a request of the master (100) which has not been granted the access right from the right grant selection controller (603a).
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: October 23, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Sho Yamanaka, Toshiyuki Hiraki, Yoshihiko Hotta, Takahiro Irita
  • Publication number: 20180286885
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Application
    Filed: June 6, 2018
    Publication date: October 4, 2018
    Inventors: Yusuke KANNO, Hiroyuki MIZUNO, Yoshihiko YASU, Kenji HIROSE, Takahiro IRITA