Abstract: Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.

Abstract: A semiconductor device according to the present invention includes a plurality of masters (100), a memory controller (400a), a bus that connects the plurality of masters (100) and the memory controller (400a), a QoS information register (610) that stores QoS information of the plurality of masters (100), a right grant number controller (602) that calculates the number of grantable access rights based on space information of a buffer (401) of the memory controller (400a), a right grant selection controller (603a) that selects the master (100) which will be granted the access right based on the QoS information of the QoS information register (610) and the number of grantable rights from the right grant number controller (602), and a request issuing controller (201a) that does not pass a request of the master (100) which has not been granted the access right from the right grant selection controller (603a).

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

Abstract: A semiconductor device according to the present invention includes a plurality of masters (100), a memory controller (400a), a bus that connects the plurality of masters (100) and the memory controller (400a), a QoS information register (610) that stores QoS information of the plurality of masters (100), a right grant number controller (602) that calculates the number of grantable access rights based on space information of a buffer (401) of the memory controller (400a), a right grant selection controller (603a) that selects the master (100) which will be granted the access right based on the QoS information of the QoS information register (610) and the number of grantable rights from the right grant number controller (602), and a request issuing controller (201a) that does not pass a request of the master (100) which has not been granted the access right from the right grant selection controller (603a).

Abstract: Disclosed is a semiconductor device capable of performing compression and decompression with increased appropriateness. The semiconductor device includes a computing module and a memory control module. The computing module includes a computing unit and a compression circuit. The computing unit performs arithmetic processing. The compression circuit compresses data indicative of the result of arithmetic processing. The memory control module includes an access circuit and a decompression circuit. The access circuit writes compressed data into a memory and reads written data from the memory. The decompression circuit decompresses data read from the memory and outputs the decompressed data to the computing module.

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

Abstract: A semiconductor apparatus according to the present invention includes a circuit including a predetermined function, a clock generating circuit that generates a clock signal supplied to the circuit, a clock control circuit that controls the clock generating circuit, and a notification signal generating circuit that generates a notification signal for notifying a timing for the clock control circuit to control the clock generating circuit. A voltage supplied to the semiconductor apparatus is adjusted according to the notification signal.

Abstract: A semiconductor device 1 includes a clock generation circuit 15 that changes a frequency of an output clock signal according to a control signal div, an arithmetic circuit (e.g., CPU0) that operates according to the clock signal, a storage circuit (e.g., IC0) that is activated according to access from the arithmetic circuit CPU0, a memory access detection unit 12 that detects a number of accesses from the arithmetic circuit CPU0 to the storage circuit IC0, and when the number of accesses increases, outputs a request signal (e.g., psreq1), and a clock control circuit 14 that generates the control signal div for lowering the frequency of the clock signal according to the request signal psreq1.

Abstract: A communication terminal according to one aspect of the present invention includes a baseband LSI that performs baseband processing for communication, an application LSI that includes a vocoder function and performs processing according to an application, an audio LSI that performs one of D/A conversion and A/D conversion on audio data, and a switch circuit that is installed in the application LSI and connects a data path between the audio processor LSI and the baseband LSI.

Abstract: A semiconductor apparatus according to the present invention includes a circuit including a predetermined function, a clock generating circuit that generates a clock signal supplied to the circuit, a clock control circuit that controls the clock generating circuit, and a notification signal generating circuit that generates a notification signal for notifying a timing for the clock control circuit to control the clock generating circuit. A voltage supplied to the semiconductor apparatus is adjusted according to the notification signal.

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

Abstract: A communication terminal according to one aspect of the present invention includes a baseband LSI that performs baseband processing for communication, an application LSI that includes a vocoder function and performs processing according to an application, an audio LSI that performs one of D/A conversion and A/D conversion on audio data, and a switch circuit that is installed in the application LSI and connects a data path between the audio processor LSI and the baseband LSI.

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

Abstract: A semiconductor device 1 includes a clock generation circuit 15 that changes a frequency of an output clock signal according to a control signal div, an arithmetic circuit (e.g., CPU0) that operates according to the clock signal, a storage circuit (e.g., IC0) that is activated according to access from the arithmetic circuit CPU0, a memory access detection unit 12 that detects a number of accesses from the arithmetic circuit CPU0 to the storage circuit IC0, and when the number of accesses increases, outputs a request signal (e.g., psreq1), and a clock control circuit 14 that generates the control signal div for lowering the frequency of the clock signal according to the request signal psreq1.

Abstract: There is a need to enable decompression of a speech signal even if no network synchronizing signal is output from a baseband processing portion. For this purpose, an information processing device includes a first serial interface. The first serial interface includes a notification signal generation circuit that generates a notification signal each time compressed data incorporated from the baseband processing portion reaches a predetermined data quantity, and notifies a speech processing portion of this state using the notification signal. The speech processing portion includes a synchronizing signal generation circuit that generates a network synchronizing signal based on the notification signal. A clock signal for PCM communication is generated based on the network synchronizing signal. A speech signal can be decompressed even if no network synchronizing signal is output from the baseband processing portion.

Abstract: A semiconductor device 1 includes a clock generation circuit 15 that changes a frequency of an output clock signal according to a control signal div, an arithmetic circuit (e.g., CPU0) that operates according to the clock signal, a storage circuit (e.g., IC0) that is activated according to access from the arithmetic circuit CPU0, a memory access detection unit 12 that detects a number of accesses from the arithmetic circuit CPU0 to the storage circuit IC0, and when the number of accesses increases, outputs a request signal (e.g., psreq1), and a clock control circuit 14 that generates the control signal div for lowering the frequency of the clock signal according to the request signal psreq1.

Abstract: There is a need to enable decompression of a speech signal even if no network synchronizing signal is output from a baseband processing portion. For this purpose, an information processing device includes a first serial interface. The first serial interface includes a notification signal generation circuit that generates a notification signal each time compressed data incorporated from the baseband processing portion reaches a predetermined data quantity, and notifies a speech processing portion of this state using the notification signal. The speech processing portion includes a synchronizing signal generation circuit that generates a network synchronizing signal based on the notification signal. A clock signal for PCM communication is generated based on the network synchronizing signal. A speech signal can be decompressed even if no network synchronizing signal is output from the baseband processing portion.

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.