Patents by Inventor Takahiro Irita

Takahiro Irita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8441095
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: May 14, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
  • Publication number: 20130053111
    Abstract: A communication terminal according to one aspect of the present invention includes a baseband LSI that performs baseband processing for communication, an application LSI that includes a vocoder function and performs processing according to an application, an audio LSI that performs one of D/A conversion and A/D conversion on audio data, and a switch circuit that is installed in the application LSI and connects a data path between the audio processor LSI and the baseband LSI.
    Type: Application
    Filed: August 19, 2012
    Publication date: February 28, 2013
    Inventors: Yutaka UCHIMURA, Takahiro IRITA, Noriaki SAKAMOTO
  • Publication number: 20130009684
    Abstract: A semiconductor apparatus according to the present invention includes a circuit including a predetermined function, a clock generating circuit that generates a clock signal supplied to the circuit, a clock control circuit that controls the clock generating circuit, and a notification signal generating circuit that generates a notification signal for notifying a timing for the clock control circuit to control the clock generating circuit. A voltage supplied to the semiconductor apparatus is adjusted according to the notification signal.
    Type: Application
    Filed: July 6, 2012
    Publication date: January 10, 2013
    Inventors: Masaki Fujigaya, Takahiro Irita
  • Publication number: 20130009687
    Abstract: A semiconductor device 1 includes a clock generation circuit 15 that changes a frequency of an output clock signal according to a control signal div, an arithmetic circuit (e.g., CPU0) that operates according to the clock signal, a storage circuit (e.g., IC0) that is activated according to access from the arithmetic circuit CPU0, a memory access detection unit 12 that detects a number of accesses from the arithmetic circuit CPU0 to the storage circuit IC0, and when the number of accesses increases, outputs a request signal (e.g., psreq1), and a clock control circuit 14 that generates the control signal div for lowering the frequency of the clock signal according to the request signal psreq1.
    Type: Application
    Filed: July 4, 2012
    Publication date: January 10, 2013
    Inventors: Tsugio MATSUYAMA, Kohei WAKAHARA, Masaki FUJIGAYA, Takahiro IRITA
  • Publication number: 20120187981
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Application
    Filed: April 3, 2012
    Publication date: July 26, 2012
    Inventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
  • Publication number: 20120109644
    Abstract: There is a need to enable decompression of a speech signal even if no network synchronizing signal is output from a baseband processing portion. For this purpose, an information processing device includes a first serial interface. The first serial interface includes a notification signal generation circuit that generates a notification signal each time compressed data incorporated from the baseband processing portion reaches a predetermined data quantity, and notifies a speech processing portion of this state using the notification signal. The speech processing portion includes a synchronizing signal generation circuit that generates a network synchronizing signal based on the notification signal. A clock signal for PCM communication is generated based on the network synchronizing signal. A speech signal can be decompressed even if no network synchronizing signal is output from the baseband processing portion.
    Type: Application
    Filed: October 31, 2011
    Publication date: May 3, 2012
    Inventors: Yutaka Uchimura, Takahiro Irita, Jiro Hara
  • Patent number: 8169036
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: May 1, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
  • Publication number: 20110320660
    Abstract: To improve processing performance of an information processing device as a whole by controlling priority in units of processes. There are provided a bus for data transfer and a plurality of function modules each having a processing function performing processing in units of processes and capable of issuing a data transfer request for the bus. Further, there is provided a process identification information holing unit capable of holding process identification information set for each of the processes in association with the function module performing processing of the process. Furthermore, there is provided a bus arbiter determining a priority order of processing for each piece of the corresponding process identification information for each data transfer request from the function module and arbitrating contention of data transfer requests for the bus according to the priority order. Processing performance is improved by performing priority order control in units of processes.
    Type: Application
    Filed: June 27, 2011
    Publication date: December 29, 2011
    Inventors: Hirotaka HARA, Tatsuya Kamei, Takahiro Irita
  • Publication number: 20110316620
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Application
    Filed: September 2, 2011
    Publication date: December 29, 2011
    Inventors: YUSUKE KANNO, HIROYUKI MIZUNO, YOSHIKIKO YASU, KENJI HIROSE, TAKAHIRO IRITA
  • Patent number: 8026570
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: September 27, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
  • Patent number: 7788469
    Abstract: A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transferred to the FPU register from a general-purpose register, and then an FPU operation is performed. For data, such as a denormalized number, that cannot be processed by the FPU, in order to call a floating-point math library of software, the processing of the BCA is completed and the processing moves to processing by software. In order to realize this, data on a data transfer bus from the CPU to the FPU is snooped by the hardware accelerator, and a cancel request is signaled to the CPU to inhibit execution of the FPU operation when corresponding data is detected in a data checking part.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: August 31, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Tetsuya Yamada, Naohiko Irie, Takahiro Irita, Masayuki Kabasawa
  • Patent number: 7774017
    Abstract: A processing load of a high performance application processing such as a voice, an image and the like is reduced, and a processing capacity of a base band processing is improved. A semiconductor integrated circuit device used in a mobile communication system such as a cellular phone is provided with a base band CPU block performing a base band processing for executing a base band protocol stack, an application system CPU block executing a high-level OS and controlling applications other than the base band processing, an application real-time CPU block executing a real-time OS and the like and controlling an image/voice processing, all of which are formed on one semiconductor chip. Further, internal high-speed buses to which these CPU blocks are connected are respectively connected via bridges.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: August 10, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Takahiro Irita, Kunihiko Nishiyama, Saneaki Tamaki, Takao Koike, Koji Goto, Masayuki Ito
  • Patent number: 7673163
    Abstract: The power supply is effectively controlled in a semiconductor integrated circuit device having a multi domain structure so as to reduce the power consumption. When an interrupt signal is inputted, the system controller makes an instruction of wakeup to the corresponding switch control unit. At this moment, the system controller controls power supply so as to be supplied sequentially from the core power source area belonging to the lower hierarchical level dependent on the core power source area to which power is supplied. The system controller outputs the power supply switch-on request signal to the switch control unit. The switch control unit turns ON the power supply switch and sends the power-on completion signal back to the system controller. Similarly, the system controller supplies power sequentially to core power source areas in the dependency relation one after another from the lower hierarchy to the upper hierarchy.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: March 2, 2010
    Assignees: Renesas Technology Corp., NTT Docomo, Inc.
    Inventors: Akifumi Tsukimori, Takahiro Irita, Hisashi Kato
  • Publication number: 20100017775
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Application
    Filed: September 24, 2009
    Publication date: January 21, 2010
    Inventors: Yusuke KANNO, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
  • Patent number: 7610572
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: October 27, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
  • Patent number: 7493479
    Abstract: A method and apparatus are provided for event detection for a multiple instruction-set processor. In one example of the apparatus, a data processing device comprises an instruction execution device configured to execute a first instruction set as specific instructions; an instruction conversion circuit configured to convert instructions of a second instruction set into a first instruction string of the first instruction set, and further configured to supply the first instruction string to the instruction execution device; and a counter device configured to count a prescribed event, wherein the instruction conversion circuit is further configured to output a prescribed instruction when the counter device is satisfied by a prescribed condition.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: February 17, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Masayuki Kabasawa, Naohiko Irie, Takahiro Irita, Tetsuya Yamada, Takanobu Tsunoda
  • Publication number: 20080218224
    Abstract: The present invention is directed to assure an initial state of a circuit until a power supply voltage is stabilized at the time of power-on and to prevent an output circuit of an external input/output buffer circuit from performing erroneous operation at the time of setting a predetermined register value or the like to an initial value. A power supply detecting circuit outputs a power supply voltage detection signal indicating that a power supply voltage supplied from the outside enters a predetermined state. A power on reset circuit receives the power supply voltage detection signal, instructs an initial setting operation of the internal circuit at a predetermined timing and, in response to completion of the initial setting operation of the internal circuit, changes an external input/output buffer circuit from a high impedance state to an operable state. Consequently, when the external input/output buffer circuit becomes operable, the initial setting of the internal circuit has already completed.
    Type: Application
    Filed: May 13, 2008
    Publication date: September 11, 2008
    Inventors: Naozumi Morino, Takahiro Irita, Yasuto Igarashi
  • Patent number: 7378887
    Abstract: The present invention is directed to assure an initial state of a circuit until a power supply voltage is stabilized at the time of power-on and to prevent an output circuit of an external input/output buffer circuit from performing erroneous operation at the time of setting a predetermined register value or the like to an initial value. A power supply detecting circuit outputs a power supply voltage detection signal indicating that a power supply voltage supplied from the outside enters a predetermined state. A power on reset circuit receives the power supply voltage detection signal, instructs an initial setting operation of the internal circuit at a predetermined timing and, in response to completion of the initial setting operation of the internal circuit, changes an external input/output buffer circuit from a high impedance state to an operable state. Consequently, when the external input/output buffer circuit becomes operable, the initial setting of the internal circuit has already completed.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: May 27, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Naozumi Morino, Takahiro Irita, Yasuto Igarashi
  • Publication number: 20070101174
    Abstract: The power supply is effectively controlled in a semiconductor integrated circuit device having a multi domain structure so as to reduce the power consumption. When an interrupt signal is inputted, the system controller makes an instruction of wakeup to the corresponding switch control unit. At this moment, the system controller controls power supply so as to be supplied sequentially from the core power source area belonging to the lower hierarchical level dependent on the core power source area to which power is supplied. The system controller outputs the power supply switch-on request signal to the switch control unit. The switch control unit turns ON the power supply switch and sends the power-on completion signal back to the system controller. Similarly, the system controller supplies power sequentially to core power source areas in the dependency relation one after another from the lower hierarchy to the upper hierarchy.
    Type: Application
    Filed: October 27, 2006
    Publication date: May 3, 2007
    Inventors: Akifumi Tsukimori, Takahiro Irita, Hisashi Kato
  • Publication number: 20070098046
    Abstract: A processing load of a high performance application processing such as a voice, an image and the like is reduced, and a processing capacity of a base band processing is improved. A semiconductor integrated circuit device used in a mobile communication system such as a cellular phone is provided with a base band CPU block performing a base band processing for executing a base band protocol stack, an application system CPU block executing a high-level OS and controlling applications other than the base band processing, an application real-time CPU block executing a real-time OS and the like and controlling an image/voice processing, all of which are formed on one semiconductor chip. Further, internal high-speed buses to which these CPU blocks are connected are respectively connected via bridges.
    Type: Application
    Filed: October 26, 2006
    Publication date: May 3, 2007
    Inventors: Takahiro Irita, Kunihiko Nishiyama, Saneaki Tamaki, Takao Koike, Koji Goto, Masayuki Ito