Patents by Inventor Takao Yonehara

Takao Yonehara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10829864
    Abstract: This disclosure enables high-productivity controlled fabrication of uniform porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: November 10, 2020
    Assignee: TruTag Technologies, Inc.
    Inventors: Karl-Josef Kramer, Mehrdad M. Moslehi, Subramanian Tamilmani, George Kamian, Jay Ashjaee, Takao Yonehara
  • Publication number: 20180347063
    Abstract: This disclosure enables high-productivity controlled fabrication of uniform porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Application
    Filed: December 21, 2017
    Publication date: December 6, 2018
    Inventors: Karl-Josef Kramer, Mehrdad M. Moslehi, Subramanian Tamilmani, George Kamian, Jay Ashjaee, Takao Yonehara
  • Patent number: 10138565
    Abstract: This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: November 27, 2018
    Assignee: TruTag Technologies, Inc.
    Inventors: Takao Yonehara, Subramanian Tamilmani, Karl-Josef Kramer, Jay Ashjaee, Mehrdad M. Moslehi, Yasuyoshi Miyaji, Noriyuki Hayashi, Takamitsu Inahara
  • Publication number: 20180323087
    Abstract: This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Application
    Filed: January 4, 2017
    Publication date: November 8, 2018
    Inventors: Takao Yonehara, Subramanian Tamilmani, Karl-Josef Kramer, Jay Ashjaee, Mehrdad M. Moslehi, Yasuyoshi Miyaji, Noriyuki Hayashi, Takamitsu Inahara
  • Patent number: 9929054
    Abstract: Methods and systems are provided for the split and separation of a layer of desired thickness of crystalline semiconductor material containing optical, photovoltaic, electronic, micro-electro-mechanical system (MEMS), or optoelectronic devices, from a thicker donor wafer using laser irradiation.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: March 27, 2018
    Inventors: Takao Yonehara, Virendra V. Rana, Sean M. Seutter, Mehrdad M. Moslehi, Subramanian Tamilmani
  • Patent number: 9890465
    Abstract: This disclosure enables high-productivity controlled fabrication of uniform porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: February 13, 2018
    Assignee: TruTag Technologies, Inc.
    Inventors: Karl-Josef Kramer, Mehrdad M. Moslehi, Subramanian Tamilmani, George D. Kamian, Jay Ashjaee, Takao Yonehara
  • Patent number: 9869031
    Abstract: This disclosure enables high-productivity fabrication of semiconductor-based separation layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers), optical reflectors (made of multi-layer/multi-porosity porous semiconductors such as porous silicon), formation of porous semiconductor (such as porous silicon) for anti-reflection coatings, passivation layers, and multi-junction, multi-band-gap solar cells (for instance, by forming a variable band gap porous silicon emitter on a crystalline silicon thin film or wafer-based solar cell). Other applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation).
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: January 16, 2018
    Assignee: OB Realty, LLC
    Inventors: George D. Kamian, Somnath Nag, Subramanian Tamilmani, Mehrdad M. Moslehi, Karl-Josef Kramer, Takao Yonehara
  • Patent number: 9870937
    Abstract: High productivity thin film deposition methods and tools are provided wherein a thin film semiconductor material layer with a thickness in the range of less than 1 micron to 100 microns is deposited on a plurality of wafers in a reactor. The wafers are loaded on a batch susceptor and the batch susceptor is positioned in the reactor such that a tapered gas flow space is created between the susceptor and an interior wall of the reactor. Reactant gas is then directed into the tapered gas space and over each wafer thereby improving deposition uniformity across each wafer and from wafer to wafer.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: January 16, 2018
    Assignee: OB Realty, LLC
    Inventors: Mehrdad M. Moslehi, Karl-Josef Kramer, Jay Ashjaee, George D. Kamian, David Mordo, Takao Yonehara
  • Publication number: 20170317225
    Abstract: Methods and systems for all wrap around porous silicon formation are provided herein. In some embodiments, a substrate holder used for all wrap around porous silicon formation may include a body having a tapered opening along a first edge of the body, wherein the tapered opening is configured to release byproduct gases produced during porous silicon formation on a substrate supported by the substrate holder, a first vacuum channel formed in the body and extending to a first surface of the body, and a first sealing element disposed on the first surface of the body and fluidly coupled to the first vacuum channel, where in the first sealing element supports the substrate when disposed thereon.
    Type: Application
    Filed: December 7, 2015
    Publication date: November 2, 2017
    Inventors: Takao YONEHARA, Pravin K. NARWANKAR, Jonathan S. FRANKEL
  • Patent number: 9771662
    Abstract: This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: September 26, 2017
    Assignee: OB REALTY, LLC
    Inventors: Takao Yonehara, Subramanian Tamilmani, Karl-Josef Kramer, Jay Ashjaee, Mehrdad M. Moslehi, Yasuyoshi Miyaji, Noriyuki Hayashi, Takamitsu Inahara
  • Publication number: 20170243774
    Abstract: Methods and apparatus for forming porous silicon layers are provided. In some embodiments, an anodizing bath includes: a housing having a first volume to hold a chemical solution; a cathode disposed within the first volume at a first side of the housing; an anode disposed within the first volume at a second side of the housing, opposite the first side, wherein a face of each of the cathode and the anode have a given surface area; a substrate holder configured to retain a plurality of substrates along a perimeter thereof within the first volume in a plurality of substrate holding positions, a plurality of vent openings fluidly coupled to the first volume to release process gases, wherein a top of each of the plurality of vent openings are disposed above a chemical solution fill level in the first volume.
    Type: Application
    Filed: September 4, 2015
    Publication date: August 24, 2017
    Inventors: Takao YONEHARA, Matthew SIMAS, Jonathan S. FRANKEL
  • Publication number: 20170243767
    Abstract: This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Application
    Filed: January 4, 2017
    Publication date: August 24, 2017
    Inventors: Takao Yonehara, Subramanian Tamilmani, Karl-Josef Kramer, Jay Ashjaee, Mehrdad M. Moslehi, Yasuyoshi Miyaji, Noriyuki Hayashi, Takamitsu Inahara
  • Publication number: 20170236954
    Abstract: Fabrication methods and structures relating to multi-level metallization for solar cells as well as fabrication methods and structures for forming back contact solar cells are provided.
    Type: Application
    Filed: April 3, 2017
    Publication date: August 17, 2017
    Inventors: Karl-Josef Kramer, Mehrdad M. Moslehi, Pawan Kapur, Virendra V. Rana, David Dutton, Sean M. Seutter, Anthony Calcaterra, Jay Ashjaee, Takao Yonehara
  • Patent number: 9523158
    Abstract: Method and apparatus for forming free-standing, substantially monocrystalline semiconductor substrates is described. A template substrate is subjected to a process of forming a porous layer on each major surface of the template substrate. The porous layer is smoothed, and then an epitaxial layer is formed on each porous layer. Mechanical energy is used to separate the epitaxial layers from the template substrate, which is recycled by removing any remaining porous and epitaxial material.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: December 20, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Takao Yonehara, Karl J. Armstrong, Fatih Mert Ozkeskin
  • Publication number: 20160336233
    Abstract: Methods and systems are provided for the split and separation of a layer of desired thickness of crystalline semiconductor material containing optical, photovoltaic, electronic, micro-electro-mechanical system (MEMS), or optoelectronic devices, from a thicker donor wafer using laser irradiation.
    Type: Application
    Filed: December 14, 2015
    Publication date: November 17, 2016
    Inventors: Takao Yonehara, Virendra V. Rana, Sean M. Seutter, Mehrdad M. Moslehi, Subramanian Tamilmani
  • Patent number: 9401276
    Abstract: An apparatus for forming porous silicon layers on at least two surfaces of a plurality of silicon templates in a batch electrochemical anodic etch process is provided. The apparatus comprises a plurality of edge-sealing template mounts operable to prevent formation of porous silicon at the edges of a plurality of templates. An electrolyte is disposed among the plurality of templates. The apparatus further comprises a power supply operable to switch polarity, change current intensity, and control etching time to produce the porous silicon layers.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: July 26, 2016
    Assignee: Solexel, Inc.
    Inventors: Mehrdad M. Moslehi, Karl-Josef Kramer, David Xuan-Qi Wang, Pawan Kapur, Somnath Nag, George D. Kamian, Jay Ashjaee, Takao Yonehara
  • Publication number: 20160186358
    Abstract: This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Application
    Filed: July 6, 2015
    Publication date: June 30, 2016
    Inventors: Takao Yonehara, Subramanian Tamilmani, Karl-Josef Kramer, Jay Ashjaee, Mehrdad M. Moslehi, Yasuyoshi Miyaji, Noriyuki Hayashi, Takamitsu Inahara
  • Patent number: 9214353
    Abstract: Methods and systems are provided for the split and separation of a layer of desired thickness of crystalline semiconductor material containing optical, photovoltaic, electronic, micro-electro-mechanical system (MEMS), or optoelectronic devices, from a thicker donor wafer using laser irradiation.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: December 15, 2015
    Assignee: Solexel, Inc.
    Inventors: Takao Yonehara, Virenda V. Rana, Sean Seutter, Mehrdad M. Moslehi, Subramanian Tamilmani
  • Publication number: 20150315719
    Abstract: This disclosure enables high-productivity fabrication of semiconductor-based separation layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers), optical reflectors (made of multi-layer/multi-porosity porous semiconductors such as porous silicon), formation of porous semiconductor (such as porous silicon) for anti-reflection coatings, passivation layers, and multi-junction, multi-band-gap solar cells (for instance, by forming a variable band gap porous silicon emitter on a crystalline silicon thin film or wafer-based solar cell). Other applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation).
    Type: Application
    Filed: April 6, 2015
    Publication date: November 5, 2015
    Inventors: George D. Kamian, Somnath Nag, Subbu Tamilmani, Mehrdad M. Moslehi, Karl-Josef Kramer, Takao Yonehara
  • Publication number: 20150308008
    Abstract: An apparatus for anodizing substrates immersed in an electrolyte solution. A substrate holder mounted in a storage tank includes a first support unit having first support elements for supporting, in a liquid-tight condition, portions of the substrates, and a second support unit attachable to and detachable from the first support unit and having second support elements for supporting, in a liquid-tight condition, the remaining portions of the substrates. The second support unit includes a first portion second support unit having support elements for supporting first portions of the remaining portions of the surfaces of the substrates, and a second portion second support unit having support elements for supporting second portions of the remaining portions of the surfaces of the substrates.
    Type: Application
    Filed: March 30, 2015
    Publication date: October 29, 2015
    Inventors: Yasuyoshi MIYAJI, Noriyuki HAYASHI, Takamitsu INAHARA, Takao YONEHARA, Karl-Josef KRAMER, Subramanian TAMILMANI