Patents by Inventor Takao Yonehara

Takao Yonehara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150225876
    Abstract: Method and apparatus for forming free-standing, substantially monocrystalline semiconductor substrates is described. A template substrate is subjected to a process of forming a porous layer on each major surface of the template substrate. The porous layer is smoothed, and then an epitaxial layer is formed on each porous layer. Mechanical energy is used to separate the epitaxial layers from the template substrate, which is recycled by removing any remaining porous and epitaxial material.
    Type: Application
    Filed: January 27, 2015
    Publication date: August 13, 2015
    Inventors: TAKAO YONEHARA, Karl J. ARMSTRONG, Fatih Mert OZKESKIN
  • Patent number: 9076642
    Abstract: This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Grant
    Filed: September 24, 2011
    Date of Patent: July 7, 2015
    Assignee: Solexel, Inc.
    Inventors: Takao Yonehara, Subramanian Tamilmani, Karl-Josef Kramer, Jay Ashjaee, Mehrdad M. Moslehi, Yasuyoshi Miyaji, Noriyuki Hayashi, Takamitsu Inahara
  • Publication number: 20150159292
    Abstract: This disclosure enables high-productivity controlled fabrication of uniform porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Application
    Filed: December 8, 2014
    Publication date: June 11, 2015
    Applicant: Solexel, Inc.
    Inventors: Karl-Josef Kramer, Mehrdad M. Moslehi, Subramanian Tamilmani, George D. Kamian, Jay Ashjaee, Takao Yonehara
  • Patent number: 8999058
    Abstract: This disclosure enables high-productivity fabrication of semiconductor-based separation layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers), optical reflectors (made of multi-layer/multi-porosity porous semiconductors such as porous silicon), formation of porous semiconductor (such as porous silicon) for anti-reflection coatings, passivation layers, and multi-junction, multi-band-gap solar cells (for instance, by forming a variable band gap porous silicon emitter on a crystalline silicon thin film or wafer-based solar cell). Other applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation).
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: April 7, 2015
    Assignee: Solexel, Inc.
    Inventors: George D. Kamian, Somnath Nag, Subbu Tamilmani, Mehrdad M. Moslehi, Karl-Josef Kramer, Takao Yonehara
  • Patent number: 8992746
    Abstract: An apparatus for anodizing substrates immersed in an electrolyte solution. A substrate holder mounted in a storage tank includes a first support unit having first support elements for supporting, in a liquid-tight condition, only lower circumferential portions of the substrates, and a second support unit attachable to and detachable from the first support unit and having second support elements for supporting, in a liquid-tight condition, remaining circumferential portions of the substrates. A drive mechanism separates the first support unit and the second support unit when loading and unloading the substrates, and for connecting the first support unit and the second support unit after the substrates are placed in the substrate holder.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: March 31, 2015
    Assignees: Dainippon Screen Mfg. Co., Ltd., Solexel, Inc.
    Inventors: Yasuyoshi Miyaji, Noriyuki Hayashi, Takamitsu Inahara, Takao Yonehara, Karl-Josef Kramer, Subramanian Tamilmani
  • Patent number: 8906218
    Abstract: This disclosure enables high-productivity controlled fabrication of uniform porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: December 9, 2014
    Assignee: Solexel, Inc.
    Inventors: Karl-Josef Kramer, Mehrdad M. Moslehi, Subramanian Tamilmani, George Kamian, Jay Ashjaee, Takao Yonehara
  • Patent number: 8871640
    Abstract: A method of manufacturing a semiconductor chip including an integrated circuit and a through-electrode penetrating a semiconductor layer includes the steps of preparing a first substrate including a release layer and a semiconductor layer formed on the release layer; forming an integrated circuit in the semiconductor layer; forming, in the semiconductor layer, a hole or groove having a depth that does not reach the release layer; filling the hole or the groove with an electrical conductor; bonding a second substrate to the semiconductor layer to form a bonded structure; separating the bonded structure at the release layer to prepare the second substrate to which the semiconductor layer is transferred; and removing at least a portion of the reverse surface side of the semiconductor layer exposed by the separation to expose the bottom of the electrical conductor.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: October 28, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takao Yonehara, Kiyofumi Sakaguchi, Nobuo Kawase, Kenji Nakagawa
  • Patent number: 8670015
    Abstract: A novel semiconductor article manufacturing method and the like are provided. A method of manufacturing a semiconductor article having a compound semiconductor multilayer film formed on a semiconductor substrate includes: preparing a member including an etching sacrificial layer (1010), a compound semiconductor multilayer film (1020), an insulating film (2010), and a semiconductor substrate (2000) on a compound semiconductor substrate (1000), and having a first groove (2005) which passes through the semiconductor substrate and the insulating film, and a semiconductor substrate groove (1025) which is a second groove provided in the compound semiconductor multilayer film so as to be connected to the first groove, and bringing an etchant into contact with the etching sacrificial layer through the first groove and then the second groove and etching the etching sacrificial layer to separate the compound semiconductor substrate from the member.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: March 11, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takao Yonehara, Kenji Yamagata, Yoshinobu Sekiguchi, Kojiro Nishi
  • Patent number: 8647923
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming a plurality of first integrated circuits on the surface side of a first semiconductor substrate; forming a plurality of second integrated circuits in a semiconductor layer that is formed on a release layer provided on a second semiconductor substrate; bonding the two semiconductor substrates so that electrically bonding portions are bonded to each other to form a bonded structure; separating the second semiconductor substrate from the bonded structure at the release layer to transfer, to the first semiconductor substrate, the semiconductor layer in which the plurality of second integrated circuits are formed; and dicing the first semiconductor substrate to obtain stacked chips each including the first integrated circuit and the second integrated circuit.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: February 11, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kiyofumi Sakaguchi, Takao Yonehara, Nobuo Kawase, Kenji Nakagawa
  • Publication number: 20140038392
    Abstract: Methods and systems are provided for the split and separation of a layer of desired thickness of crystalline semiconductor material containing optical, photovoltaic, electronic, micro-electro-mechanical system (MEMS), or optoelectronic devices, from a thicker donor wafer using laser irradiation.
    Type: Application
    Filed: February 26, 2013
    Publication date: February 6, 2014
    Inventors: Takao Yonehara, Virenda V. Rana, Sean Seutter, Mehrdad M. Moslehi, Subramanian Tamilmani
  • Patent number: 8617922
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming a plurality of first integrated circuits on the surface side of a first semiconductor substrate; forming a plurality of second integrated circuits in a semiconductor layer that is formed on a release layer provided on a second semiconductor substrate; bonding the two semiconductor substrates so that electrically bonding portions are bonded to each other to form a bonded structure; separating the second semiconductor substrate from the bonded structure at the release layer to transfer, to the first semiconductor substrate, the semiconductor layer in which the plurality of second integrated circuits are formed; and dicing the first semiconductor substrate to obtain stacked chips each including the first integrated circuit and the second integrated circuit.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: December 31, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kiyofumi Sakaguchi, Takao Yonehara, Nobuo Kawase, Kenji Nakagawa
  • Patent number: 8513093
    Abstract: According to a method for transferring a functional region, at least part of functional regions on separation layers arranged on a first substrate is transferred onto a second substrate, the separation layers being capable of being brought into a separable state by treatment. In a first bonding step, the first substrate is bonded to the second substrate with a dry film resist arranged between the second substrate and the at least part of the functional regions above the first substrate. In an exposure step, at least part of the dry film resist is exposed. In a patterning step, the exposed dry film resist is patterned.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: August 20, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takao Yonehara
  • Patent number: 8507360
    Abstract: A method includes arranging a bonding layer of a predetermined thickness on at least one of a first functional region bonded on a release layer, which is capable of falling into a releasable condition when subjected to a process, on a first substrate, and a region, to which the first functional region is to be transferred, on a second substrate; bonding the first functional region to the second substrate through the bonding layer; and separating the first substrate from the first functional region at the release layer.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: August 13, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takao Yonehara, Yasuyoshi Takai
  • Publication number: 20130180847
    Abstract: This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.
    Type: Application
    Filed: September 24, 2011
    Publication date: July 18, 2013
    Inventors: Takao Yonehara, Subramanian Tamilmani, Karl-Josef Kramer, Jay Ashjaee, Mehrdad M. Moslehi, Yasuyoshi Miyaji, Noriyuki Hayashi, Takamitsu Inahara
  • Publication number: 20130171808
    Abstract: This disclosure presents manufacturing methods and apparatus designs for making TFSSs from both sides of a re-usable semiconductor template, thus effectively increasing the substrate manufacturing throughput and reducing the substrate manufacturing cost. This approach also reduces the amortized starting template cost per manufactured substrate (TFSS) by about a factor of 2 for a given number of template reuse cycles.
    Type: Application
    Filed: July 20, 2012
    Publication date: July 4, 2013
    Applicant: SOLEXEL, INC.
    Inventors: Mehrdad M. Moslehi, Karl-Josef Kramer, David Xuan-Qi Wang, Pawan Kapur, Somnath Nag, George D. Kamian, Jay Ashjaee, Takao Yonehara
  • Patent number: 8432425
    Abstract: A light-emitting unit having an arrayed light source comprises a substrate; an arrayed light source group containing the arrayed light source arranged in a first direction; a lens array for focusing the light emitted from light emitting elements constituting the arrayed light source; and a lens support having a cavity formed between arrayed light source group and the lens array; the lens support having a first hole for introducing a fluid into the cavity, and a second hole for discharging the introduced fluid in a second direction crossing the first direction.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: April 30, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takao Yonehara
  • Patent number: 8420501
    Abstract: A method includes arranging a first bonding layer on a first functional region on a first substrate, or a region on a second substrate, bonding the first functional region to the second substrate through the first bonding layer, subjecting a first release layer to a first process to separate the first substrate from the first functional region at the first release layer, arranging a second bonding layer on a second functional region on the first substrate, or a region on a third substrate, bonding the second functional region to the second or third substrate through the second bonding layer, and subjecting a second release layer to a second process to separate the first substrate from the second functional region at the second release layer.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: April 16, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takao Yonehara, Yasuyoshi Takai
  • Patent number: 8415230
    Abstract: Provided is a method for transferring, onto a second substrate, at least one of functional regions arranged and joined to a first separation layer that is disposed on a first substrate and that becomes separable by a treatment, in which regions on the second substrate where the functional regions are to be transferred have a second separation layer that becomes separable by a treatment. The method includes a step of joining the first substrate to the second substrate by bonding such that the functional regions contact the second separation layer; a step of separating the functional regions from the first substrate at the first separation layer; and a step of, before or after the step of separation, forming separation grooves penetrating through the second substrate and the second separation layer from a surface of the second substrate, the surface being opposite to a surface having the second separation layer thereon.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: April 9, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takao Yonehara, Yasuyoshi Takai
  • Publication number: 20120282716
    Abstract: A novel semiconductor article manufacturing method and the like are provided. A method of manufacturing a semiconductor article having a compound semiconductor multilayer film formed on a semiconductor substrate includes: preparing a member including an etching sacrificial layer (1010), a compound semiconductor multilayer film (1020), an insulating film (2010), and a semiconductor substrate (2000) on a compound semiconductor substrate (1000), and having a first groove (2005) which passes through the semiconductor substrate and the insulating film, and a semiconductor substrate groove (1025) which is a second groove provided in the compound semiconductor multilayer film so as to be connected to the first groove, and bringing an etchant into contact with the etching sacrificial layer through the first groove and then the second groove and etching the etching sacrificial layer to separate the compound semiconductor substrate from the member.
    Type: Application
    Filed: July 16, 2012
    Publication date: November 8, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Takao Yonehara, Kenji Yamagata, Yoshinobu Sekiguchi, Kojiro Nishi
  • Patent number: 8241940
    Abstract: This disclosure presents manufacturing methods and apparatus designs for making TFSSs from both sides of a re-usable semiconductor template, thus effectively increasing the substrate manufacturing throughput and reducing the substrate manufacturing cost. This approach also reduces the amortized starting template cost per manufactured substrate (TFSS) by about a factor of 2 for a given number of template reuse cycles.
    Type: Grant
    Filed: February 12, 2011
    Date of Patent: August 14, 2012
    Assignee: Solexel, Inc.
    Inventors: Mehrdad M. Moslehi, Karl-Josef Kramer, David Xuan-Qi Wang, Pawan Kapur, Somnath Nag, George D Kamian, Jay Ashjaee, Takao Yonehara