Patents by Inventor Takashi Chiba

Takashi Chiba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5914180
    Abstract: A magnetic recording medium having a thin magnetic metal film formed by vapor deposition under an atmosphere of an introduced oxygen gas. The thickness of the surface oxide film having the degree of oxidation of 50% or higher is maintained so as to be not higher than 5% of the total film thickness of the thin magnetic metal film. The magnetic recording medium is affected to a lesser extent by the surface oxide layer such that it is superior in magnetic properties, such as coercivity, and in electromagnetic properties.
    Type: Grant
    Filed: September 21, 1995
    Date of Patent: June 22, 1999
    Assignee: Sony Corporation
    Inventors: Jota Ito, Takashi Chiba, Kenichi Sato, Hidetoshi Honda, Toshiharu Uchimi, Taketoshi Sato, Yukihiro Koshika, Yasumi Sato
  • Patent number: 5125081
    Abstract: A configuration control system for changing a system configuration of a data processing system. The configuration control system has a plurality of clusters and at least one global storage unit. Each of the clusters has a channel processing unit, at least one central processing unit, at least one main storage unit, a memory control unit and a service processor. The at least one global storage unit has the plural clusters in common. The configuration control system includes a first configuration control device for holding connection information of each unit in a cluster; and a second configuration control device for holding configuration control information of the global storage unit and the cluster. The second configuration control device controlled independently to the first configuration control device.
    Type: Grant
    Filed: February 23, 1989
    Date of Patent: June 23, 1992
    Assignee: Fujitsu Limited
    Inventor: Takashi Chiba
  • Patent number: 4871901
    Abstract: A coffee roasting apparatus is disclosed. The coffee roasting apparatus comprises a cylindrical container, a cylindrical drum rotatably extended within the center portion of the container, and a heater element diposed within the drum. The apparatus includes a blower device to cause air circulation within the interior of the container to more uniformily heat the beans. The heater element is controlled by a control device to reduce the calorific value of the heater element when the temperature of the container reaches a predetermined temperature. Therefore, abnormal temperature in the container is prevented, while the roasting operation is speedily done. A control device for the blower device is also disclosed which will vary the speed of the blower in response to changes in the input voltage. In this way, an increase in the input voltage which may have caused unwanted overheating is avioded by a corresponding increase in air circulation.
    Type: Grant
    Filed: June 25, 1986
    Date of Patent: October 3, 1989
    Assignee: Sanden Corporation
    Inventors: Masaru Igusa, Takashi Chiba
  • Patent number: 4866603
    Abstract: A memory access control system has a main memory having a plurality of memory banks divided into two groups, thus enabling parallel processing for data, a command/address bus line, a write data bus line, a read data bus line, and a device for simultaneously activating one request for access to the memory bank belonging to one group and another request for access to the memory bank belonging to the other group.
    Type: Grant
    Filed: January 20, 1988
    Date of Patent: September 12, 1989
    Assignee: Fujitsu Limited
    Inventor: Takashi Chiba
  • Patent number: 4760546
    Abstract: A tag control circuit is provided in a memory access control apparatus of a digital computer system which also includes a central processor having a buffer storage. The tag control circuit includes a tag information store and update circuit and a necessity operation circuit for determining whether invalidation of the tag information and whether transmission of an invalidation information to the central processor are necessary. The tag control circuit also includes a first storage for storing a plurality of access requests of the invalidation operation determined by the necessity operation circuit, a second storage for storing a plurality of invalidation execute information determined by the necessity operation circuit, and a selection circuit receiving a new access request and an access request stored in the first storage and outputting one access request.
    Type: Grant
    Filed: June 19, 1985
    Date of Patent: July 26, 1988
    Assignee: Fujitsu Limited
    Inventors: Miyuki Ishida, Takashi Chiba
  • Patent number: 4589064
    Abstract: A data processing apparatus includes at least one processing unit, a main storage unit, a main storage control unit, a key storage unit and a key storage control unit. The main storage unit is divided into blocks and the key storage unit stores main storage protection keys, each of which corresponds to one of the blocks of the main storage unit. Key storage access requests are received from a processing unit or the main storage control unit by the key storage control unit whenever data is to be read from or written to a block of main storage. The key storage control unit registers the key storage access requests in a key queue, prevents duplicate access requests from being registered, and processes the queued key storage access requests. The processing of key storage access requests includes updating the contents of the key storage unit to maintain a record of accesses to the main storage unit and controlling accesses to the main storage unit by permitting or denying access thereto.
    Type: Grant
    Filed: February 25, 1983
    Date of Patent: May 13, 1986
    Assignee: Fujitsu Limited
    Inventors: Takashi Chiba, Satoru Koga, Minji Senda
  • Patent number: 4453216
    Abstract: A computer system comprising a plurality of channels, at least one main storage unit, and a memory control unit having a channel buffer between the main storage unit and the channels. The channel buffer comprises a memory portion divided into a plurality of tag blocks, tag lines, and a data memory portion having a plurality of data lines each corresponding to one of the tag lines. Two tag lines forming a set and each set of the tag memory portion is assigned to one of the channels.
    Type: Grant
    Filed: June 14, 1982
    Date of Patent: June 5, 1984
    Assignee: Fujitsu Limited
    Inventors: Takashi Chiba, Satoru Koga
  • Patent number: 4115855
    Abstract: For extracting a unit data block of the lowest priority from a plurality of unit data blocks stored in a buffer memory of large capacity, the unit data blocks are divided into set blocks, each comprising a predetermined number of unit data blocks, and priority levels of the set blocks are determined to extract one of them. At the same time, priority levels of the predetermined number of unit data blocks making up each set block are determined to extract one of them. One unit data block is extracted by a combination of the extracted set block with the unit data blocks extracted from the respective set blocks. In this manner, one of many unit data blocks is extracted by using a small number of bits.
    Type: Grant
    Filed: August 19, 1976
    Date of Patent: September 19, 1978
    Assignee: Fujitsu Limited
    Inventor: Takashi Chiba
  • Patent number: D357393
    Type: Grant
    Filed: April 12, 1994
    Date of Patent: April 18, 1995
    Assignee: Nitto Kohki Co., Ltd.
    Inventors: Yasuo Kazama, Takashi Chiba