Patents by Inventor Takashi Hase

Takashi Hase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160267975
    Abstract: A semiconductor memory includes a memory cell including a resistance change element and a control circuit configured to perform OFF-write processing of applying an OFF-write pulse to the memory cell for switching the state of the memory cell to a high-resistive state where a resistance value of the resistance change element is at least a first reference value and ON-write processing of applying an ON-write pulse to the memory cell for switching the state of the memory cell to a low-resistive state where the resistance value is less than a second reference value. The control circuit performs the OFF-write processing by applying an auxiliary pulse which is smaller than the OFF-write pulse in voltage amplitude to the memory cell one or more time(s) after having applied the OFF-write pulse to the memory cell.
    Type: Application
    Filed: December 9, 2015
    Publication date: September 15, 2016
    Inventors: Kiyoshi TAKEUCHI, Takashi Hase
  • Publication number: 20160111627
    Abstract: A vibration device that includes a vibration portion, a support portion connected to the vibration portion, a bending-vibrating portion connected to the support portion, and a frame-shaped base portion connected to the bending-vibration portion and disposed so as to surround the vibration portion. The base portion defines a slit that extends in a first direction crossing a second direction in which the support portion extends from the vibration portion, the slit defining first and second fixed ends of the bending-vibrating portion and which are continuous with the base portion. A length between a portion of the bending-vibrating portion connected to the support portion to one of the first and second fixed ends of the bending-vibrating portion is in a range of ?/8 to 3?/8, where ? denotes a wavelength of a bending vibration corresponding to a frequency of a characteristic vibration of the vibration portion.
    Type: Application
    Filed: December 22, 2015
    Publication date: April 21, 2016
    Inventors: Takashi Hase, Toshio Nishimura, Hiroaki Kaida
  • Publication number: 20160079426
    Abstract: To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1×1016/cm3, and includes a group III nitride compound. A well is a p-type impurity layer and formed in the compound semiconductor layer. A source region is formed within the well and is an n-type impurity layer. A low-concentration n-type region is formed in the compound semiconductor layer and is linked to the well. A drain region is formed in the compound semiconductor layer and is located on a side opposite to the well via the low-concentration n-type region. The drain region is an n-type impurity layer.
    Type: Application
    Filed: November 25, 2015
    Publication date: March 17, 2016
    Inventors: Ippei KUME, Hiroshi TAKEDA, Toshiharu NAGUMO, Takashi HASE
  • Publication number: 20160072473
    Abstract: A vibrating device having a number 2N (N is an integer equal to 2 or larger) of tuning fork arms extending in a first direction are arranged side by side in a second direction. Phases of flexural vibrations of the number N of tuning fork arms positioned at a first side of an imaginary line A, which passes a center of a region in the second direction where the number 2N of tuning fork arms are disposed and which extends in the first direction, are symmetric to phases of flexural vibrations of the number N of tuning fork arms positioned at a second side of the imaginary line opposite the first side.
    Type: Application
    Filed: November 5, 2015
    Publication date: March 10, 2016
    Inventors: Toshio Nishimura, Takashi Hase, Keisuke Takeyama, Hiroaki Kaida, Keiichi Umeda, Takehiko Kishi, Hiroshi Yamada
  • Publication number: 20160065173
    Abstract: A vibrating device having tuning fork arms extending in a first direction that are joined to a base portion and are arranged side by side in an second direction. Each of the tuning fork arms has a structure that a silicon oxide layer is laminated on a Si layer made of a degenerate semiconductor, and that an excitation portion is provided on the silicon oxide layer. When a total thickness of the Si layer is denoted by T1, a total thickness of the silicon oxide layer is denoted by T2, and the temperature coefficient of resonant frequency (TCF) when the silicon oxide layer is not provided on the Si layer is denoted by x, a thickness ratio T2/(T1+T2) is within a range of (?0.0002x2?0.0136x+0.0014)±0.05.
    Type: Application
    Filed: November 10, 2015
    Publication date: March 3, 2016
    Inventors: TOSHIO NISHIMURA, Takashi Hase, Keisuke Takeyama, Hiroaki Kaida, Keiichi Umeda, Takehiko Kishi, Hiroshi Yamada
  • Publication number: 20160064642
    Abstract: A vibrating device that is in the form of a rectangular plate having opposed long sides and opposed short sides, and that utilizes an expanding and contracting vibration mode in a direction of the short sides. The vibrating device includes a Si layer made of a degenerate semiconductor, a silicon oxide layer, a piezoelectric layer, and first and second electrodes through which a voltage is applied to the piezoelectric layer. When a total thickness of the Si layer is denoted by T1, a total thickness of the silicon oxide layer is denoted by T2, and the TCF in the vibrating device when the silicon oxide layer 3 is not provided is denoted by x(ppm/K), T2/(T1+T2) is within a range of (?0.0003x2?0.0256x+0.0008)±0.05.
    Type: Application
    Filed: November 12, 2015
    Publication date: March 3, 2016
    Inventors: TOSHIO NISHIMURA, Keiichi Umeda, Takashi Hase, Keisuke Takeyama, Takehiko Kishi, Hiroshi Yamada
  • Publication number: 20160056145
    Abstract: Performance of a semiconductor device is improved. The semiconductor device includes a substrate composed of silicon, a semiconductor layer composed of p-type nitride semiconductor provided on the substrate, and a transistor including a channel layer provided on the semiconductor layer. The semiconductor device further includes an n-type source region provided in the channel layer, and an n-type drain region provided in the channel layer separately from the source region in a plan view. Each of the source region and the drain region is in contact with the semiconductor layer.
    Type: Application
    Filed: August 17, 2015
    Publication date: February 25, 2016
    Inventors: Toshiharu Nagumo, Takashi Hase, Kiyoshi Takeuchi, Ippei Kume
  • Publication number: 20160049375
    Abstract: A semiconductor device includes a substrate which includes a first face. The device also includes a buffer layer, a semiconductor layer, source and drain electrodes, and a gate electrode. A trench is formed on the semiconductor layer so that the trench surrounds the source electrode, the drain electrode, and the gate electrode in a plan view, the trench passes through the semiconductor layer and the buffer layer, and a bottom of the trench reaches at least an inside of the substrate. A distance from the first face of the substrate to the bottom of the trench is 100 nm or more in a thickness direction of the substrate.
    Type: Application
    Filed: October 28, 2015
    Publication date: February 18, 2016
    Inventors: Ippei KUME, Takashi ONIZAWA, Takashi HASE, Shigeru HIRAO, Tadatoshi DANNO
  • Patent number: 9254493
    Abstract: The invention is characterized in: forming a magnetic field inside a flow channel tube, the tube wall of which is formed from a material that is nonmagnetic and which, when the pressure outside the flow channel tube is lower than the pressure inside the flow channel tube, passes a portion of the air flowing inside the tube through the tube wall and discharges same to the outside thereof; supplying air to the flow channel tube so that at least a region of laminar flow is formed inside the flow channel tube; and reducing the pressure outside the flow channel tube to a prescribed pressure.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: February 9, 2016
    Assignee: Kobe Steel, Ltd.
    Inventors: Kenichi Inoue, Takashi Hase, Shingo Kasai
  • Publication number: 20160005792
    Abstract: Provided is a semiconductor memory device (resistance random access memory element) improved in properties. A Ru film is formed as a film of a lower electrode by sputtering, and a Ta film is formed thereonto by sputtering. Next, the Ta film is oxidized with plasma to oxidize the Ta film. In this way, a compound Ta2O5 is produced and further Ru is diffused into the compound to form a layer (variable resistance layer) in which Ru is diffused into the compound Ta2O5. Such an incorporation of a metal (such as Ru) into a transition metal oxide TMO (such as Ta2O5) makes it possible to form electron conductive paths additional to filaments to lower the filaments in density and thickness. Thus, the memory element can be restrained from undergoing OFF-fixation, by which the element is not easily lowered in resistance, to be improved in ON-properties.
    Type: Application
    Filed: June 25, 2015
    Publication date: January 7, 2016
    Inventors: Makoto UEKI, Nobuyuki IKARASHI, Jun KAWAHARA, Kiyoshi TAKEUCHI, Takashi HASE
  • Patent number: 9231105
    Abstract: To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1×1016/cm3, and includes a group III nitride compound. A well is a p-type impurity layer and formed in the compound semiconductor layer. A source region is formed within the well and is an n-type impurity layer. A low-concentration n-type region is formed in the compound semiconductor layer and is linked to the well. A drain region is formed in the compound semiconductor layer and is located on a side opposite to the well via the low-concentration n-type region. The drain region is an n-type impurity layer.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: January 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Ippei Kume, Hiroshi Takeda, Toshiharu Nagumo, Takashi Hase
  • Patent number: 9196731
    Abstract: Sometimes to warp a group III nitride semiconductor and a silicon by the stress of the group III nitride semiconductor acting on the silicon. A semiconductor device includes a substrate, a buffer layer, and a semiconductor layer. A trench is formed on a sixth face of the semiconductor layer. The trench passes through the semiconductor layer and the buffer layer. The bottom of the trench reaches at least the inside of the substrate.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: November 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Ippei Kume, Takashi Onizawa, Takashi Hase, Shigeru Hirao, Tadatoshi Danno
  • Patent number: 9160219
    Abstract: Disclosed is a brushless motor (1A) which is an axial gap type brushless motor (1A) wherein stators (3A, 4A) comprising a coil (41) and a rotor (2) comprising a permanent magnet (23) are arranged with a gap therebetween in the axial direction. The coil (41) is a band-like wire which is spirally wound such that the width direction of the band-like wire generally coincides with the direction of the magnetic flux that is generated by the permanent magnet (23) of the rotor (2). Consequently, the axial gap type brushless motor (1A) having the above-described structure can be further reduced in eddy current loss in comparison to conventional brushless motors.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: October 13, 2015
    Assignee: Kobe Steel, Ltd.
    Inventors: Hiroyuki Takamatsu, Koji Inoue, Kenichi Inoue, Takashi Hase, Osamu Ozaki, Chikara Ichihara, Masakatsu Maruyama, Yasushi Maeda, Hiroyuki Mitani
  • Publication number: 20150279923
    Abstract: To provide a semiconductor device having less variation in characteristics. The semiconductor device is equipped with a plug formed in an interlayer insulating film, a lower electrode provided on the plug and to be coupled to the plug, a middle layer provided on the lower electrode and made of a metal oxide, and an upper electrode provided on the middle layer. The middle layer has a layered region contiguous to the lower electrode and the upper electrode. At least a portion of the layered region does not overlap with the plug. At least a portion of the plug does not overlap with the layered region.
    Type: Application
    Filed: March 18, 2015
    Publication date: October 1, 2015
    Inventors: Makoto UEKI, Kiyoshi TAKEUCHI, Takashi HASE
  • Publication number: 20150180449
    Abstract: A vibrating device having vibrating arms connected to a supporter. The vibrating arms have an n-type Si layer which is a degenerated semiconductor and an exciter provided on the n-type Si layer. The exciter has a piezoelectric thin film and a first and second electrodes with the piezoelectric thin film interposed therebetween.
    Type: Application
    Filed: March 10, 2015
    Publication date: June 25, 2015
    Inventors: Keiichi Umeda, Takehiko Kishi, Toshio Nishimura, Takashi Hase
  • Publication number: 20150060875
    Abstract: To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1×1016/cm3, and includes a group III nitride compound. A well is a p-type impurity layer and formed in the compound semiconductor layer. A source region is formed within the well and is an n-type impurity layer. A low-concentration n-type region is formed in the compound semiconductor layer and is linked to the well. A drain region is formed in the compound semiconductor layer and is located on a side opposite to the well via the low-concentration n-type region. The drain region is an n-type impurity layer.
    Type: Application
    Filed: August 21, 2014
    Publication date: March 5, 2015
    Inventors: Ippei Kume, Hiroshi Takeda, Toshiharu Nagumo, Takashi Hase
  • Publication number: 20150060942
    Abstract: Sometimes to warp a group III nitride semiconductor and a silicon by the stress of the group III nitride semiconductor acting on the silicon. A semiconductor device includes a substrate, a buffer layer, and a semiconductor layer. A trench is formed on a sixth face of the semiconductor layer. The trench passes through the semiconductor layer and the buffer layer. The bottom of the trench reaches at least the inside of the substrate.
    Type: Application
    Filed: August 8, 2014
    Publication date: March 5, 2015
    Inventors: Ippei Kume, Takashi Onizawa, Takashi Hase, Shigeru Hirao, Tadatoshi Danno
  • Patent number: 8729778
    Abstract: An electromechanical transducer that includes an elongating/contracting member and a driving member. The elongating/contracting member elongates and contracts in response to application of a voltage thereto. The elongating/contracting member has a side surface that is parallel to an elongation/contraction direction. The driving member is provided on the side surface of the elongating/contracting member. The driving member is displaced with elongation and contraction of the elongating/contracting member.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: May 20, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masanaga Nishikawa, Takashi Hase, Toshio Nishimura
  • Publication number: 20140013950
    Abstract: The invention is characterized in: forming a magnetic field inside a flow channel tube, the tube wall of which is formed from a material that is nonmagnetic and which, when the pressure outside the flow channel tube is lower than the pressure inside the flow channel tube, passes a portion of the air flowing inside the tube through the tube wall and discharges same to the outside thereof; supplying air to the flow channel tube so that at least a region of laminar flow is formed inside the flow channel tube; and reducing the pressure outside the flow channel tube to a prescribed pressure.
    Type: Application
    Filed: May 8, 2012
    Publication date: January 16, 2014
    Applicant: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel Ltd.)
    Inventors: Kenichi Inoue, Takashi Hase, Shingo Kasai
  • Publication number: 20130271960
    Abstract: To provide a semiconductor light emitting device which is capable of accomplishing a broad color reproducibility for an entire image without losing brightness of the entire image. A light source provided on a backlight for a color image display device has a semiconductor light emitting device comprising a solid light emitting device to emit light in a blue or deep blue region or in an ultraviolet region and phosphors, in combination. The phosphors comprise a green emitting phosphor and a red emitting phosphor. The green emitting phosphor and the red emitting phosphor are ones, of which the rate of change of the emission peak intensity at 100° C. to the emission intensity at 25° C., when the wavelength of the excitation light is 400 nm or 455 nm, is at most 40%.
    Type: Application
    Filed: June 10, 2013
    Publication date: October 17, 2013
    Inventors: Byungchul HONG, Naoki SAKO, Naoto KIJIMA, Masahiko YOSHINO, Takashi HASE, Fumiko YOYASU, Kentarou HORIBE