Patents by Inventor Takashi Hase
Takashi Hase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090152640Abstract: This invention provides a semiconductor device that can prevent a deviation of work function by adopting a gate electrode having a uniform composition and exhibits excellent operating characteristics by virtue of effective control of a Vth. The semiconductor device is characterized by comprising a PMOS transistor, an NMOS transistor, a gate insulating film comprising an Hf-containing insulating film with high permittivity, a line electrode comprising a silicide region (A) and a silicide region (B), one of the silicide regions (A) and (B) comprising a silicide (a) of a metal M, which serves as a diffusing species in a silicidation reaction, the other silicide region comprising a silicide layer (C) in contact with a gate insulating film, the silicide layer (C) comprising a silicide (b) of a metal M, which has a smaller atom composition ratio of the metal M than the silicide (a), and a dopant which can substantially prevent diffusion of the metal M in the silicide (b).Type: ApplicationFiled: December 26, 2006Publication date: June 18, 2009Applicant: NEC CORPORATIONInventor: Takashi Hase
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Publication number: 20090115002Abstract: There is provided a semiconductor device including: a first field effect transistor region including a gate insulating film, a gate electrode and gate sidewalls formed in a P channel forming region; and a second field effect transistor region including a gate insulating film, a gate electrode and gate sidewalls formed in an N channel forming region on a semiconductor substrate, wherein in the first and second field effect transistor regions, the gate electrodes are composed primarily of a silicide of metal M represented as M(x)Si(1?x)(0<x<1) and satisfy t1?t2<L/2, wherein the height of the gate electrodes is t1, the height of the gate sidewalls is t2 and the gate length of the gate electrodes is L; and the height of the gate electrode in the P channel forming region is greater than the height of the gate electrode in the N channel forming region.Type: ApplicationFiled: June 20, 2006Publication date: May 7, 2009Applicant: NEC CORPORATIONInventors: Tooru Tatsumi, Masayuki Terai, Takashi Hase, Kensuke Takahashi
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Publication number: 20090072255Abstract: The present invention relates to a phosphor that satisfies requirements (1) to (3): (1) the phosphor satisfies Formula [2] and/or Formula [3]: 85?{R455(125)/R455(25)}×100<110??[2] 92?{R405(100)/R405(25)}×100<110??[3] wherein R455(125) represents an emission peak intensity when the phosphor is excited by light having a peak wavelength of 455 nm at 125° C., (2) the emission peak wavelength is in the range of 570 nm to 680 nm, and (3) the full width at half maximum of an emission peak is 90 nm or less. The phosphor of the present invention has a high luminous efficiency and emits light of orange to red with high luminance. The use of the phosphor makes it possible to produce a light-emitting device, an illumination apparatus, and an image display, having a high efficiency and excellent color rendering properties.Type: ApplicationFiled: August 10, 2006Publication date: March 19, 2009Applicant: Mitsubishi Chemical CorporationInventors: Tomoko Takahashi, Nobuhiro Kodama, Yasuo Shimomura, Naoto Kijima, Tomoyuki Kurushima, Takashi Hase, Eiji Hattori, Kouichi Adachi, Keiichi Seki, Yutaka Mori
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Publication number: 20080287303Abstract: A precursor for producing a Nb3Sn superconducting wire includes a bundle of single-element wires each including a Cu or Cu-based alloy matrix, Nb or Nb-based alloy filaments, at least one Sn or Sn-based alloy core, the Nb or Nb-based alloy filaments and at least one Sn or Sn-based alloy core being arranged in the Cu or Cu-based alloy matrix, an diffusion barrier layer around the periphery of the Cu or Cu-based alloy matrix, the inner diffusion barrier layer being composed of Nb or a Nb-based alloy, and a Cu or Cu-based alloy layer around the periphery of the diffusion barrier layer; an outer diffusion barrier layer around the periphery of the bundle of the single-element wires, the outer diffusion barrier layer being composed of Nb, a Nb-based alloy, Ta, a Ta-based alloy, or a combination thereof; and a stabilizing copper layer around the periphery of the outer diffusion barrier layer.Type: ApplicationFiled: April 16, 2008Publication date: November 20, 2008Inventors: Hiroyuki Kato, Takashi Hase, Kyoji Zaitsu
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Patent number: 7446454Abstract: An energy-trapping-type thickness extensional piezoelectric resonator using a thickness extensional vibration mode having first and second resonance electrodes formed on portions of the top surface and the bottom surface of a piezoelectric substrate that is polarized in the thickness direction thereof, respectively, in which a portion where the first and second resonance electrodes oppose each other is formed as an energy-trapping-type vibration section, wherein, in order to suppress frequency changes of the thickness extensional vibration mode due to temperature, which is a main response using resonance characteristics, a suppression response having a frequency-temperature-change tendency for suppressing frequency changes of the main response due to temperature is brought into close proximity with the main response.Type: GrantFiled: November 29, 2006Date of Patent: November 4, 2008Assignee: Murata Manufacturing Co., Ltd.Inventors: Hiroaki Kaida, Hitoshi Sakaguchi, Takashi Hase, Jiro Inoue
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Publication number: 20080227280Abstract: According to the present invention, it is provided a method of manufacturing a semiconductor device comprising a PMOS transistor and an NMOS transistor, wherein the method facilitates obtaining a full silicide phase of a suitable composition for the NMOS transistor and the PMOS transistor respectively, with fewer mask layers and through a fewer number of manufacturing steps.Type: ApplicationFiled: March 14, 2008Publication date: September 18, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Takashi HASE
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Publication number: 20080227279Abstract: According to the present invention, it is provided a method of manufacturing a semiconductor device comprising a PMOS transistor and a NMOS transistor, wherein the method facilitates obtaining a FUSI phase of a suitable composition for the NMOS transistor and the PMOS transistor respectively, with fewer mask layers and through a fewer number of manufacturing stepsType: ApplicationFiled: March 14, 2008Publication date: September 18, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Takashi HASE
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Publication number: 20080227278Abstract: A method of manufacturing a semiconductor device including an NMOS transistor and a PMOS transistor is provided. The method includes: forming a silicon layer over a substrate through a gate insulating film; forming a first gate electrode and a second gate electrode by patterning the silicon layer, the first gate electrode being a gate electrode of the NMOS transistor, and the second gate electrode being a gate electrode of the PMOS transistor; selectively forming a silicon oxide film on the first gate electrode which is formed of silicon; after the selectively forming the silicon oxide film, forming a first metallic layer formed of a metal capable of forming a silicide over the first and second gate electrodes; and performing a first heat treatment such that a first silicide layer of a silicide of the first metallic layer is formed.Type: ApplicationFiled: March 12, 2008Publication date: September 18, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Takashi HASE
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Publication number: 20080179994Abstract: An energy trap piezoelectric resonator makes use of a harmonic wave in a thickness longitudinal vibration mode and can effectively suppress a spurious fundamental wave in a thickness longitudinal vibration mode without significantly suppressing the harmonic wave that is used for the resonator. The energy trap piezoelectric resonator has a first excitation electrode disposed at an upper surface of a piezoelectric substrate polarized in a thickness direction and a second excitation electrode disposed at a lower surface, and a floating electrode disposed at least one of the upper surface and/or the lower surface of the piezoelectric substrate so as to extend towards and away from the first excitation electrode with respect to a node of an electric potential distribution based on electric charges generated by the fundamental wave that is propagated when an energy trap vibration portion where the excitation electrodes oppose each other is excited.Type: ApplicationFiled: April 20, 2005Publication date: July 31, 2008Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Hitoshi Sakaguchi, Hiroaki Kaida, Takashi Hase
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Publication number: 20080167192Abstract: A precursor for fabricating a Nb3Sn superconducting wire by an internal Sn process includes one or a plurality of stabilizing copper portions collectively disposed in the center, each stabilizing copper portion being provided with a diffusion barrier layer in the periphery thereof, and a superconducting matrix portion disposed so as to surround the one or the plurality of stabilizing copper portions, the superconducting matrix portion including a Nb or Nb-based alloy core and a Sn or Sn-based alloy core embedded in a Cu or Cu-based alloy matrix.Type: ApplicationFiled: September 21, 2007Publication date: July 10, 2008Inventors: Hiroyuki Kato, Takashi Hase, Kyoji Zaitsu
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Patent number: 7291530Abstract: A method of manufacturing a semiconductor storage device having a capacitive element having a dielectric layer having a perovskite-type crystal structure represented by general formula ABO3 and a lower electrode and an upper electrode disposed so as to sandwich the dielectric layer therebetween; in the method are carried out forming, on a lower electrode conductive layer, using a MOCVD method, an initial nucleus containing at least one metallic element the same as a metallic element in the dielectric layer, forming, on the initial nucleus, using a MOCVD method, a buffer layer containing at least one metallic element the same as the metallic element contained in both the initial nucleus and the dielectric layer, in a higher content than the content of this metallic element contained in the initial nucleus, and forming, on the buffer layer, using a MOCVD method, the dielectric layer having a perovskite-type crystal structure.Type: GrantFiled: August 12, 2005Date of Patent: November 6, 2007Assignee: NEC Electronics CorporationInventors: Takashi Nakagawa, Takashi Hase
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Patent number: 7271054Abstract: A ferroelectric capacitor has the property that polarization of a ferroelectric thin film can readily be reversed and polarization-reversal charge increased. The ferroelectric capacitor has a bottom electrode, a ferroelectric thin film and a top electrode. The top electrode includes a metal crystalline phase and 0.5 to 5 atm % interstitial oxygen atoms in the metal crystalline phase.Type: GrantFiled: February 11, 2005Date of Patent: September 18, 2007Assignee: NEC Electronics CorporationInventor: Takashi Hase
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Publication number: 20070163675Abstract: A precursor for manufacturing a Nb3Sn superconducting wire by bronze method, in which plural Nb or Nb-based alloy cores are buried in a Cu—Sn-based alloy base material. The Cu—Sn-based alloy base material comprises Ti and/or Zr in addition to Sn, and these components satisfy the equations (1) and (2) below: 0.4?(X?15.6)/Y?1.9??(1) and 15.6<X?19 ??(2) where the symbol X denotes the content of Sn in mass % and the symbol Y denotes the total content of Ti and Zr in mass %.Type: ApplicationFiled: November 7, 2006Publication date: July 19, 2007Inventors: Takashi Hase, Yukinobu Murakami, Hiroyuki Yasunaka, Takayoshi Miyazaki, Hiroyuki Kato, Kyoji Zaitsu
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Publication number: 20070069608Abstract: An energy-trapping-type thickness extensional piezoelectric resonator using a thickness extensional vibration mode having first and second resonance electrodes formed on portions of the top surface and the bottom surface of a piezoelectric substrate that is polarized in the thickness direction thereof, respectively, in which a portion where the first and second resonance electrodes oppose each other is formed as an energy-trapping-type vibration section, wherein, in order to suppress frequency changes of the thickness extensional vibration mode due to temperature, which is a main response using resonance characteristics, a suppression response having a frequency-temperature-change tendency for suppressing frequency changes of the main response due to temperature is brought into close proximity with the main response.Type: ApplicationFiled: November 29, 2006Publication date: March 29, 2007Inventors: Hiroaki Kaida, Hitoshi Sakaguchi, Takashi Hase, Jiro Inoue
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Publication number: 20050287735Abstract: A method of manufacturing a semiconductor storage device having a capacitive element having a dielectric layer having a perovskite-type crystal structure represented by general formula ABO3 and a lower electrode and an upper electrode disposed so as to sandwich the dielectric layer therebetween; in the method are carried out forming, on a lower electrode conductive layer, using a MOCVD method, an initial nucleus containing at least one metallic element the same as a metallic element in the dielectric layer, forming, on the initial nucleus, using a MOCVD method, a buffer layer containing at least one metallic element the same as the metallic element contained in both the initial nucleus and the dielectric layer, in a higher content than the content of this metallic element contained in the initial nucleus, and forming, on the buffer layer, using a MOCVD method, the dielectric layer having a perovskite-type crystal structure.Type: ApplicationFiled: August 12, 2005Publication date: December 29, 2005Applicant: NEC Electronics CorporationInventors: Takashi Nakagawa, Takashi Hase
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Patent number: 6958504Abstract: A method of manufacturing a semiconductor storage device having a capacitive element having a dielectric layer having a perovskite-type crystal structure represented by general formula ABO3 and a lower electrode and an upper electrode disposed so as to sandwich the dielectric layer therebetween; in the method are carried out forming, on a lower electrode conductive layer, using a MOCVD method, an initial nucleus containing at least one metallic element the same as a metallic element in the dielectric layer, forming, on the initial nucleus, using a MOCVD method, a buffer layer containing at least one metallic element the same as the metallic element contained in both the initial nucleus and the dielectric layer, in a higher content than the content of this metallic element contained in the initial nucleus, and forming, on the buffer layer, using a MOCVD method, the dielectric layer having a perovskite-type crystal structure.Type: GrantFiled: June 8, 2004Date of Patent: October 25, 2005Assignee: NEC Electronics CorporationInventors: Takashi Nakagawa, Takashi Hase
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Patent number: 6872995Abstract: A ferroelectric capacitor has the property that polarization of a ferroelectric thin film can readily be reversed and polarization-reversal charge increased. The ferroelectric capacitor has a bottom electrode, a ferroelectric thin film and a top electrode. The top electrode includes a metal crystalline phase and 0.5 to 5 atm % interstitial oxygen atoms in the metal crystalline phase.Type: GrantFiled: April 28, 2003Date of Patent: March 29, 2005Assignee: NEC Electronics CorporationInventor: Takashi Hase
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Patent number: 6863726Abstract: A vapor phase growth method of an oxide dielectric film for forming an oxide dielectric film having a perovskite crystal structure expressed by ABO3 on a substrate according to the present invention includes a first step of sequentially and alternately supplying an A-site layer element material and a B-site layer element material to grow an atomic layer on the substrate to form an early layer or early core, at a first substrate temperature, and a second step of raising the temperature to a second substrate temperature that is higher than the first substrate temperature to crystallize the early layer or early core formed in the first step and simultaneously supplying both the A-site layer element material and the B-site layer element material to form an ABO3 film.Type: GrantFiled: April 22, 2003Date of Patent: March 8, 2005Assignee: NEC Electronics CorporationInventor: Takashi Hase
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Publication number: 20040253746Abstract: A method of manufacturing a semiconductor storage device having a capacitive element having a dielectric layer having a perovskite-type crystal structure represented by general formula ABO3 and a lower electrode and an upper electrode disposed so as to sandwich the dielectric layer therebetween; in the method are carried out forming, on a lower electrode conductive layer, using a MOCVD method, an initial nucleus containing at least one metallic element the same as a metallic element in the dielectric layer, forming, on the initial nucleus, using a MOCVD method, a buffer layer containing at least one metallic element the same as the metallic element contained in both the initial nucleus and the dielectric layer, in a higher content than the content of this metallic element contained in the initial nucleus, and forming, on the buffer layer, using a MOCVD method, the dielectric layer having a perovskite-type crystal structure.Type: ApplicationFiled: June 8, 2004Publication date: December 16, 2004Applicant: NEC Electronics CorporationInventors: Takashi Nakagawa, Takashi Hase
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Patent number: 6753099Abstract: The present invention provides a green emitting phosphor which includes an excess of the ordinary SiO2 component included in parent material Y2−2xSiO5 activated by Tb in terms of stoichiometric ratio. The composition of the above phosphor is represented by chemical formula: {(Y1−y−zMyGdz)1−xTbx}2(Si1−bGebO2)1+aO3 where values of x, y, z, a, and b are assigned, subject to 0<x≦1, 0≦y≦1, 0≦z≦1, 0<a≦1, and 0≦b≦1, and M is at least one element selected from a group comprising Sc, In, La, Lu, Yb, Ce, Eu, Sm, Tm, Ho, Er, and Nd. By using this phosphor, phosphors that emit light of higher luminance with less luminance degradation and are suitable for high-quality image display and imaging devices producing high-quality images are obtained.Type: GrantFiled: June 27, 2002Date of Patent: June 22, 2004Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd., Kasei Optonix, Ltd.Inventors: Shin Imamura, Masatoshi Shiiki, Masaaki Komatsu, Hidetsugu Matsukiyo, Yoshihiro Koseki, Takashi Hase, Tsutomu Yamada