Patents by Inventor Takashi Hase
Takashi Hase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8491816Abstract: To provide a semiconductor light emitting device which is capable of accomplishing a broad color reproducibility for an entire image without losing brightness of the entire image. A light source provided on a backlight for a color image display device has a semiconductor light emitting device comprising a solid light emitting device to emit light in a blue or deep blue region or in an ultraviolet region and phosphors, in combination. The phosphors comprise a green emitting phosphor and a red emitting phosphor. The green emitting phosphor and the red emitting phosphor are ones, of which the rate of change of the emission peak intensity at 100° C. to the emission intensity at 25° C., when the wavelength of the excitation light is 400 nm or 455 nm, is at most 40%.Type: GrantFiled: February 6, 2009Date of Patent: July 23, 2013Assignee: Mitsubishi Chemical CorporationInventors: Byungchul Hong, Naoki Sako, Naoto Kijima, Masahiko Yoshino, Takashi Hase, Fumiko Yoyasu, Kentarou Horibe
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Publication number: 20130009508Abstract: Disclosed is a brushless motor (1A) which is an axial gap type brushless motor (1A) wherein stators (3A, 4A) comprising a coil (41) and a rotor (2) comprising a permanent magnet (23) are arranged with a gap therebetween in the axial direction. The coil (41) is a band-like wire which is spirally wound such that the width direction of the band-like wire generally coincides with the direction of the magnetic flux that is generated by the permanent magnet (23) of the rotor (2). Consequently, the axial gap type brushless motor (1A) having the above-described structure can be further reduced in eddy current loss in comparison to conventional brushless motors.Type: ApplicationFiled: December 6, 2010Publication date: January 10, 2013Applicant: KABUSHIKI KAISHA KOBE SEIKO SHO (Kobe Steel, Ltd.)Inventors: Hiroyuki Takamatsu, Koji Inoue, Kenichi Inoue, Takashi Hase, Osamu Ozaki, Chikara Ichihara, Masakatsu Maruyama, Yasushi Maeda, Hiroyuki Mitani
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Patent number: 8330234Abstract: In a semiconductor device, a gate electrode having a uniform composition prevents deviation in a work function. Controlling a Vth provides excellent operation properties. The semiconductor device includes an NMOS transistor and a PMOS transistor with a common line electrode. The line electrode includes electrode sections (A) and (B) and a diffusion barrier region formed over an isolation region so that (A) and (B) are kept out of contact. The diffusion barrier region meets at least one of: (1) The diffusion coefficient in the above diffusion barrier region of the constituent element of the above electrode section (A) is lower than the interdiffusion coefficient of the constituent element between electrode section (A) materials; and (2) The diffusion coefficient in the above diffusion barrier region of the constituent element of the above electrode section (B) is lower than the interdiffusion coefficient of the constituent element between electrode section (B) materials.Type: GrantFiled: November 21, 2006Date of Patent: December 11, 2012Assignee: NEC CorporationInventor: Takashi Hase
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Patent number: 8277687Abstract: The present invention relates to a phosphor that satisfies requirements (1) to (3): (1) the phosphor satisfies Formula [2] and/or Formula [3]: 85?{R455(125)/R455(25)}×100?110??[2] 92?{R405(100)/R405(25)}×100?110??[3] wherein R455(125) represents an emission peak intensity when the phosphor is excited by light having a peak wavelength of 455 nm at 125° C., (2) the emission peak wavelength is in the range of 570 nm to 680 nm, and (3) the full width at half maximum of an emission peak is 90 nm or less. The phosphor of the present invention has a high luminous efficiency and emits light of orange to red with high luminance. The use of the phosphor makes it possible to produce a light-emitting device, an illumination apparatus, and an image display, having a high efficiency and excellent color rendering properties.Type: GrantFiled: August 10, 2006Date of Patent: October 2, 2012Assignee: Mitsubishi Chemical CorporationInventors: Tomoko Takahashi, Nobuhiro Kodama, Yasuo Shimomura, Naoto Kijima, Tomoyuki Kurushima, Takashi Hase, Eiji Hattori, Kouichi Adachi, Keiichi Seki, Yutaka Mori
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Publication number: 20120228997Abstract: An electromechanical transducer that includes an elongating/contracting member and a driving member. The elongating/contracting member elongates and contracts in response to application of a voltage thereto. The elongating/contracting member has a side surface that is parallel to an elongation/contraction direction. The driving member is provided on the side surface of the elongating/contracting member. The driving member is displaced with elongation and contraction of the elongating/contracting member.Type: ApplicationFiled: May 18, 2012Publication date: September 13, 2012Applicant: Murata Manufacturing Co., Ltd.Inventors: Masanaga Nishikawa, Takashi Hase, Toshio Nishimura
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Publication number: 20110207272Abstract: A process for manufacturing a semiconductor device includes preparing a semiconductor substrate including an N-type region and a P-type region isolated by an isolation region, forming a gate insulating film including an Hf-containing high-dielectric insulating film at least in an uppermost surface over the semiconductor substrate, forming a silicon layer over the gate insulating film, implanting a dopant into only any one of silicon layers over the P-type region and the N-type region, processing the silicon layers to form a gate pattern including a silicon region extending from a region over the N-type region through a region over the isolation region to a region over the P-type region, forming a gate sidewall on a sidewall of the gate pattern, implanting a dopant into the semiconductor substrate using the gate pattern and the gate sidewall as a mask, activating the dopant in the silicon region and the semiconductor substrate by heating, forming an interlayer insulating film over the gate pattern, removing thType: ApplicationFiled: April 27, 2011Publication date: August 25, 2011Applicant: NEC CORPORATIONInventor: Takashi Hase
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Patent number: 7985714Abstract: A precursor for fabricating a Nb3Sn superconducting wire by an internal Sn process includes one or a plurality of stabilizing copper portions collectively disposed in the center, each stabilizing copper portion being provided with a diffusion barrier layer in the periphery thereof, and a superconducting matrix portion disposed so as to surround the one or the plurality of stabilizing copper portions, the superconducting matrix portion including a Nb or Nb-based alloy core and a Sn or Sn-based alloy core embedded in a Cu or Cu-based alloy matrix.Type: GrantFiled: September 21, 2007Date of Patent: July 26, 2011Assignee: Kobe Steel, Ltd.Inventors: Hiroyuki Kato, Takashi Hase, Kyoji Zaitsu
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Patent number: 7968947Abstract: This invention provides a semiconductor device that can prevent a deviation of work function by adopting a gate electrode having a uniform composition and exhibits excellent operating characteristics by virtue of effective control of a Vth. The semiconductor device is characterized by comprising a PMOS transistor, an NMOS transistor, a gate insulating film comprising an Hf-containing insulating film with high permittivity, a line electrode comprising a silicide region (A) and a silicide region (B), one of the silicide regions (A) and (B) comprising a silicide (a) of a metal M, which serves as a diffusing species in a silicidation reaction, the other silicide region comprising a silicide layer (C) in contact with a gate insulating film, the silicide layer (C) comprising a silicide (b) of a metal M, which has a smaller atom composition ratio of the metal M than the silicide (a), and a dopant which can substantially prevent diffusion of the metal M in the silicide (b).Type: GrantFiled: December 26, 2006Date of Patent: June 28, 2011Assignee: NEC CorporationInventor: Takashi Hase
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Patent number: 7883983Abstract: A method of manufacturing a semiconductor device, includes: forming a gate insulating film on a semiconductor substrate; forming a first metal film on the gate insulating film; forming a second metal film on the first metal film; and patterning a stacked film of the first and second metal films such that the stacked film is left in a gate electrode formation region and a resistive element formation region. The method further includes: removing the second metal film in the resistive element formation region with protecting a contact hole formation region. The method further includes: forming an interlayer insulating film so as to cover the stacked film; and removing the interlayer insulating film formed in the contact hole formation region to form a contact hole leading to the second metal film.Type: GrantFiled: May 18, 2009Date of Patent: February 8, 2011Assignee: Renesas Electronics CorporationInventor: Takashi Hase
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Patent number: 7858462Abstract: A method of manufacturing a semiconductor device including an NMOS transistor and a PMOS transistor is provided. The method includes: forming a silicon layer over a substrate through a gate insulating film; forming a first gate electrode and a second gate electrode by patterning the silicon layer, the first gate electrode being a gate electrode of the NMOS transistor, and the second gate electrode being a gate electrode of the PMOS transistor; selectively forming a silicon oxide film on the first gate electrode which is formed of silicon; after the selectively forming the silicon oxide film, forming a first metallic layer formed of a metal capable of forming a silicide over the first and second gate electrodes; and performing a first heat treatment such that a first silicide layer of a silicide of the first metallic layer is formed.Type: GrantFiled: March 12, 2008Date of Patent: December 28, 2010Assignee: Renesas Electronics CorporationInventor: Takashi Hase
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Publication number: 20100213822Abstract: In order to improve quantum efficiency and/or durability of phosphors, a complex oxynitride phosphor is provided represented by the following formula, which can be obtained by firing a phosphor precursor in the presence of flux. M1xBayM2zLuOvNw (In the formula, M1 represents at least one kind of activation element selected from the group consisting of Mn, Ce, Pr, Nd, Sm, Eu, Tb, Dy, Ho, Er, Tm and Yb, M2 represents at least one kind of bivalent metal element selected from the group consisting of Sr, Ca, Mg and Zn, L represents a metal element selected from the metal elements belonging to the fourth group or the fourteenth group of the periodic table, and 0.00001?x?3, 0?y?2.99999, 2.6?x+y+z?3, 0<u?11, 6<v?25, and 0<w?17.Type: ApplicationFiled: July 31, 2008Publication date: August 26, 2010Inventors: Satoshi Shimooka, Kyota Ueda, Naoto Kijima, Takashi Hase, Chisato Shimooka, Hiromu Watanabe, Tomoyuki Kurushima
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Patent number: 7781319Abstract: According to the present invention, it is provided a method of manufacturing a semiconductor device comprising a PMOS transistor and a NMOS transistor, wherein the method facilitates obtaining a FUSI phase of a suitable composition for the NMOS transistor and the PMOS transistor respectively, with fewer mask layers and through a fewer number of manufacturing steps.Type: GrantFiled: March 14, 2008Date of Patent: August 24, 2010Assignee: NEC Electronics CorporationInventor: Takashi Hase
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Patent number: 7776673Abstract: According to the present invention, it is provided a method of manufacturing a semiconductor device comprising a PMOS transistor and an NMOS transistor, wherein the method facilitates obtaining a full silicide phase of a suitable composition for the NMOS transistor and the PMOS transistor respectively, with fewer mask layers and through a fewer number of manufacturing steps.Type: GrantFiled: March 14, 2008Date of Patent: August 17, 2010Assignee: NEC Electronics CorporationInventor: Takashi Hase
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Publication number: 20100193883Abstract: Provided is a semiconductor device of the present invention including, a substrate; a Hf-containing insulating film (HfSiON film) provided over the semiconductor substrate; a NiSi fully-silicided electrode for blocking diffusion of at least Hf which composes the insulating film and a metal element which composes the fully-silicided gate electrode, provided over the HfSiON film; and a barrier film (SiOC film) provided between HfSiON film and the NiSi fully-silicided electrode so as to be brought into contact with the NiSi fully-silicided electrode, wherein the NiSi fully-silicided electrode contains either an N-type or a P-type impurity segregated in a portion thereof brought into contact with the SiOC film, and the SiOC film has a dielectric constant not larger than that of a silicon oxynitride film, and contains (i) silicon (Si), (ii) carbon (C), and (iii) oxygen (O) or nitrogen (N), as major constituents.Type: ApplicationFiled: February 3, 2010Publication date: August 5, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: TAKASHI HASE
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Publication number: 20100142189Abstract: To provide a semiconductor light emitting device which is capable of accomplishing a broad color reproducibility for an entire image without losing brightness of the entire image. A light source provided on a backlight for a color image display device has a semiconductor light emitting device comprising a solid light emitting device to emit light in a blue or deep blue region or in an ultraviolet region and phosphors, in combination. The phosphors comprise a green emitting phosphor and a red emitting phosphor. The green emitting phosphor and the red emitting phosphor are ones, of which the rate of change of the emission peak intensity at 100° C. to the emission intensity at 25° C., when the wavelength of the excitation light is 400 nm or 455 nm, is at most 40%.Type: ApplicationFiled: February 6, 2009Publication date: June 10, 2010Applicant: MITSUBISHI CHEMICAL CORPORATIONInventors: Byungchul Hong, Naoki Sako, Naoto Kijima, Masahiko Yoshino, Takashi Hase, Fumiko Yoyasu, Kentarou Horibe
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Patent number: 7723176Abstract: Element characteristics disadvantageously fluctuate because the composition of the resultant silicide varies according to the change of the gate length when a full silicide gate electrode is formed by sintering a metal/poly-Si structure. The element characteristics also fluctuate due to element-to-element non-uniformity of the resultant silicide composition. By first forming full silicide having a metal-rich composition, depositing a Si layer thereon, and sintering the combined structure, the metal in the metal-rich silicide diffuses into the Si layer, so that the Si layer is converted into silicide. The entire structure thus is converted into full silicide having a smaller metal composition ratio.Type: GrantFiled: August 29, 2006Date of Patent: May 25, 2010Assignee: NEC CorporationInventor: Takashi Hase
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Publication number: 20090286378Abstract: A method of manufacturing a semiconductor device, comprises: forming a gate insulating film on a semiconductor substrate; forming a first metal film on the gate insulating film; forming a second metal film on the first metal film; and patterning a stacked film of the first and second metal films such that the stacked film is left in a gate electrode formation region and a resistive element formation region. The method further comprises: removing the second metal film in the resistive element formation region with protecting a contact hole formation region. The method further comprises: forming an interlayer insulating film so as to cover the stacked film; and removing the interlayer insulating film formed in the contact hole formation region to form a contact hole leading to the second metal film.Type: ApplicationFiled: May 18, 2009Publication date: November 19, 2009Applicant: NEC ELECTRONICS CORPORATIONInventor: Takashi HASE
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Publication number: 20090267158Abstract: There is provided a semiconductor device in which deviation in a work function is prevented by a gate electrode having a uniform composition and which has excellent operation properties by effectively controlling a Vth. The semiconductor device comprises an NMOS transistor and a PMOS transistor with a common line electrode, characterized in that the line electrode comprise an electrode section (A), an electrode section (B) and a diffusion barrier region formed in a part over an isolation region so that the electrode sections (A) and (B) are kept out of contact and the diffusion barrier region meets at least one of the following conditions (1) and (2). (1) The diffusion coefficient D1 in the above diffusion barrier region of the constituent element A? of the above electrode section (A) is lower than the interdiffusion coefficient D2 of the constituent element A? between electrode section (A) materials.Type: ApplicationFiled: November 21, 2006Publication date: October 29, 2009Applicant: NEC CORPORATIONInventor: Takashi Hase
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Publication number: 20090221116Abstract: Element characteristics disadvantageously fluctuate because the composition of the resultant silicide varies according to the change of the gate length when a full silicide gate electrode is formed by sintering a metal/poly-Si structure. The element characteristics also fluctuate due to element-to-element non-uniformity of the resultant silicide composition. By first forming full silicide having a metal-rich composition, depositing a Si layer thereon, and sintering the combined structure, the metal in the metal-rich silicide diffuses into the Si layer, so that the Si layer is converted into silicide. The entire structure thus is converted into full silicide having a smaller metal composition ratio.Type: ApplicationFiled: August 29, 2006Publication date: September 3, 2009Inventor: Takashi Hase
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Patent number: 7567014Abstract: An energy trap piezoelectric resonator makes use of a harmonic wave in a thickness longitudinal vibration mode and can effectively suppress a spurious fundamental wave in a thickness longitudinal vibration mode without significantly suppressing the harmonic wave that is used for the resonator. The energy trap piezoelectric resonator has a first excitation electrode disposed at an upper surface of a piezoelectric substrate polarized in a thickness direction and a second excitation electrode disposed at a lower surface, and a floating electrode disposed at at least one of the upper surface and/or the lower surface of the piezoelectric substrate so as to extend towards and away from the first excitation electrode with respect to a node of an electric potential distribution based on electric charges generated by the fundamental wave that is propagated when an energy trap vibration portion where the excitation electrodes oppose each other is excited.Type: GrantFiled: April 20, 2005Date of Patent: July 28, 2009Assignee: Murata Manufacturing Co., Ltd.Inventors: Hitoshi Sakaguchi, Hiroaki Kaida, Takashi Hase