Patents by Inventor Takashi Inoue

Takashi Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8749463
    Abstract: A phase-modulating apparatus includes a spatial light modulator, an input value setting unit, a plurality of sets of reference data, a converting unit, and a driving unit. The input value setting unit sets an input value for each pixel. Each set of reference data corresponds to at least one pixel. The converting unit converts an input value inputted for each pixel to a control value by referencing the corresponding set of reference data. The driving unit converts the control value to a voltage value. The driving unit drives each pixel with a drive voltage corresponding to the voltage value. Each set of reference data correlates a plurality of first values from which input values are taken, and a plurality of second values from which control values are taken to ensure that the relationship between the plurality of first values and phase modulation amounts attained by the corresponding at least one pixel is a prescribed linear relationship.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: June 10, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Naoya Matsumoto, Takashi Inoue, Norihiro Fukuchi, Yuji Kobayashi, Tsutomu Hara
  • Publication number: 20140153274
    Abstract: At least a part of light emitted from a light source fixed to a heat sink 11 passes through a projection lens 14. A first screw 81 having a first manipulation portion 81a and a second screw 91 having a second manipulation portion 91a extend through the heat sink 11. A reference position of an optical axis Ax is adjusted in a first direction by manipulating the first manipulation portion 81a. The reference position of the optical axis Ax is adjusted in a second direction intersecting the first direction by manipulating the second manipulation portion 91a. Of the heat sink 11, at least a portion in which the first manipulation portion 81a and the second manipulation portion 91a are disposed, is disposed outside the housing 2.
    Type: Application
    Filed: December 3, 2013
    Publication date: June 5, 2014
    Applicant: KOITO MANUFACTURING CO., LTD.
    Inventors: Hiroki Shibata, Takashi Inoue, Masashi Tatsukawa
  • Patent number: 8716755
    Abstract: Compression strains are generated at an interface between the cap layer and the barrier layer and an interface between the channel layer and the buffer layer and a tensile strain is generated at an interface between the barrier layer and the channel layer. Therefore, negative charge is higher than positive charge at the interface between the cap layer and the barrier layer and the interface between the channel layer and the buffer layer, while positive charge is higher than negative charge at the interface between the barrier layer and the channel. The channel layer has a stacked layer structure of a first layer, a second layer, and a third layer. The second layer has a higher electron affinity than those of the first layer and the third layer.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: May 6, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hironobu Miyamoto
  • Patent number: 8716835
    Abstract: A bipolar transistor is provided with an emitter layer, a base layer and a collector layer. The emitter layer is formed above a substrate and is an n-type conductive layer including a first nitride semiconductor. The base layer is formed on the emitter layer and is a p-type conductive including a second nitride semiconductor. The collector layer is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed such that a crystal growth direction to the substrate surface is parallel to a substrate direction of [000-1]. The third nitride semiconductor contains InycAlxcGa1-xc-ycN (0•xc•1, 0•yc•1, 0<xc+yc•1). The a-axis length on the side of a surface in the third nitride semiconductor is shorter than the a-axis length on the side of the substrate.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: May 6, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yuji Ando, Hironobu Miyamoto, Tatsuo Nakayama, Yasuhiro Okamoto, Takashi Inoue, Kazuki Ota
  • Publication number: 20140116997
    Abstract: A laser machining apparatus includes a main control unit executing NC program; a laser oscillator oscillating laser light according to instruction from the main control unit; a distance sensor measuring distance L between a nozzle and a workpiece; a sensor-data processing unit sampling a measured value of the distance sensor; and a copying control unit moving a machining head to maintain the distance constant based the measured value, wherein the sensor-data processing unit samples the measured value with an operation period shorter than that of the main control unit and, when a portion corresponding to the through hole in the workpiece comes off and the distance becomes larger than a predetermined value during the inner hole machining, causes oscillation of laser light to be stopped by outputting a stop signal to the laser oscillator.
    Type: Application
    Filed: September 20, 2012
    Publication date: May 1, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventor: Takashi Inoue
  • Patent number: 8695110
    Abstract: In a near-field scanning microscope using an aperture probe, the upper limit of the aperture formation is at most several ten nm in practice. In a near-field scanning microscope using a scatter probe, the resolution ability is limited to at most several ten nm because of the external illuminating light serving as background noise. Moreover, measurement reproducibility is seriously lowered by a damage or abrasion of a probe. Optical data and unevenness data of the surface of a sample can be measured at a nm-order resolution ability and a high reproducibility while damaging neither the probe nor the sample by fabricating a plasmon-enhanced near-field probe having a nm-order optical resolution ability by combining a nm-order cylindrical structure with nm-order microparticles and repeatedly moving the probe toward the sample and away therefrom at a low contact force at individual measurement points on the sample.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: April 8, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Toshihiko Nakata, Masahiro Watanabe, Takashi Inoue, Kishio Hidaka, Motoyuki Hirooka
  • Patent number: 8687067
    Abstract: An object of the present invention is to simplify a calibration operation of a camera and to shorten a time necessary for calibration. A camera calibration device 10 is mounted on a predetermined position of a movable object 100 and includes a camera 11 configured to take an image including an index 41 provided outside the movable object 100, an image superimposing unit 122 configured to generate a superimposed image by superimposing a calibration object 42 having a position adjustment part and a rotation adjustment part on the image taken by the camera 11, and a calculation unit 124 configured to calculate, based on a position of the calibration object 42 after being shifted in the superimposed image such that an end or a center of the index 41 meets the position adjustment part and a part of the index other than the end or the center overlaps the rotation adjustment part, parameters relative to a pan angle, a tilt angle and a roll angle for calibration of the camera mounting position.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: April 1, 2014
    Assignee: KYOCERA Corporation
    Inventors: Takeo Oshima, Takashi Maekawa, Ryuuichi Sawada, Haruo Yanagisawa, Chinatsu Sakurai, Akinori Iwabuchi, Shinya Tamizu, Takashi Inoue
  • Publication number: 20140084300
    Abstract: A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1-zAlzN (0?z?1), a channel layer having a composition of: AlxGa1-xN (0?x?1) or InyGa1-yN (0?y?1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.
    Type: Application
    Filed: May 15, 2012
    Publication date: March 27, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasuhiro Okamoto, Yuji Ando, Tatsuo Nakayama, Takashi Inoue, Kazuki Ota
  • Patent number: 8674407
    Abstract: The present invention provides a semiconductor device having such a structure formed by sequentially laminating a lower barrier layer composed of lattice-relaxed AlxGa1-xN (0?x?1), a channel layer composed of InyGa1-yN (0?y?1) with compressive strain and a contact layer composed of AlzGa1-zN (0?z?1), wherein a two-dimensional electron gas is produced in the vicinity of an interface of said InyGa1-yN channel layer with said AlzGa1-zN contact layer; a gate electrode is formed so as to be embedded in the recessed portion with intervention of an insulating film, which recessed portion is formed by removing a part of said AlzGa1-zN contact layer by etching it away until said InyGa1-yN channel layer is exposed; and, ohmic electrodes are formed on the AlzGa1-zN contact layer. Thus, the semiconductor device has superior uniformity and reproducibility of the threshold voltage while maintaining a low gate leakage current, and is also applicable to the enhancement mode type.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: March 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yuji Ando, Yasuhiro Okamoto, Kazuki Ota, Takashi Inoue, Tatsuo Nakayama, Hironobu Miyamoto
  • Patent number: 8674409
    Abstract: A heterojunction filed effect transistor with a low access resistance, a low on resistance, and the like, a method for producing a heterojunction filed effect transistor and an electron device are provided.
    Type: Grant
    Filed: December 25, 2009
    Date of Patent: March 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Inoue, Hironobu Miyamoto, Kazuki Ota, Tatsuo Nakayama, Yasuhiro Okamoto, Yuji Ando
  • Patent number: 8668225
    Abstract: A vehicle seat includes: a seat back frame that is provided with a pair of side frame portions that are located on both left and right sides in the seat transverse direction; an outer-side load transmitting block that is located further to an outer side in the transverse direction of the seat back frame than the side frame portion of the seat back frame, and that transmits an impact load that is input from a side of the vehicle body to the seat back frame; a protruding portion that protrudes from a side surface of the side frame portion on the outer side in the transverse direction of the seat back frame towards the outer side in the transverse direction of the seat back frame; a side airbag apparatus that is located on a front surface of the protruding portion; and an engaging portion that is formed in the outer-side load transmitting block, and that receives the protruding portion.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: March 11, 2014
    Assignees: Honda Motor Co., Ltd., Tachi-S Co., Ltd.
    Inventors: Jogen Yamaki, Hisato Oku, Takashi Inoue, Takuya Hori, Masato Miyaguchi, Kazuyoshi Arata
  • Patent number: 8661996
    Abstract: A sewing machine auxiliary storage compartment is provided that can be attached to or detached from a sewing machine body part and that allows small articles such as accessories to be taken out therefrom or put thereinto even during sewing. Upper and lower parts are attached slidably with respect to each other. The upper part 11 is provided with an attachment part 116 that can be attached to the sewing machine body part by its one end. The lower part 12 is attached to the upper part 11 slidably in a direction crossing a workpiece feeding direction when the upper part 11 and the sewing machine body part are attached together. A storage part 122 for storing accessories is provided in the lower part 12, which is located on the opposite side to the one end.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: March 4, 2014
    Assignee: Jaguar International Corporation
    Inventor: Takashi Inoue
  • Patent number: 8659055
    Abstract: Provided is a semiconductor device capable of suppressing an occurrence of a punch-through phenomenon. A semiconductor device includes a substrate 1, a first n-type semiconductor layer 2, a p-type semiconductor layer 3, a second n-type semiconductor layer 4, a drain electrode 13, a source electrode 11, a gate electrode 12, and a gate insulation film 21, wherein the first n-type semiconductor layer 2, the p-type semiconductor layer 3, and the second n-type semiconductor layer 4 are laminated on the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 2. The source electrode 11 is in ohmic-contact with the second n-type semiconductor layer 4. An opening portion to be filled or a notched portion that extends from an upper surface of the second n-type semiconductor layer 4 to an upper part of the first n-type semiconductor layer 2 is formed at a part of the p-type semiconductor layer 3 and a part of the second n-type semiconductor layer 4.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: February 25, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Okamoto, Kazuki Ota, Takashi Inoue, Hironobu Miyamoto, Tatsuo Nakayama, Yuji Ando
  • Patent number: 8659303
    Abstract: A testing apparatus for testing whether an occupant detection sensor normally operates is disclosed. The testing apparatus includes: a ground that is an electrically-conductive structural member of the seat; an electrode plate that is electrically-conductive and is on the seat at a time of testing; multiple capacitors that are electrically connected between the electrode plate and the ground and are different in electrostatic capacity from each other; a switch mechanism that selects and switches one capacitor of the multiple capacitors; and a determination result check portion that determines, while switching the one capacitor by the switch mechanism, whether a signal outputted from the occupant detection sensor is a determination result corresponding to the switched one capacitor.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: February 25, 2014
    Assignee: Denso Corporation
    Inventors: Hideyuki Hayakawa, Takashi Inoue
  • Publication number: 20140036182
    Abstract: The present invention relates to a phase modulating apparatus capable of highly accurately and easily correcting the phase modulation characteristic of a reflective electric address spatial light modulator even when a condition of input light is changed. In the LCOS phase modulating apparatus, an input unit inputs the condition of the input light, and a processing unit sets an input value for each pixel. A correction value deriving unit determines a correction condition according to the condition of the input light. A control input value converting unit converts the input value set for each pixel into a corrected input value based on the correction condition. An LUT processing unit converts the corrected input value into a voltage value, and drives each pixel by using a drive voltage equivalent to the converted voltage value.
    Type: Application
    Filed: October 3, 2013
    Publication date: February 6, 2014
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Naoya MATSUMOTO, Norihiro FUKUCHI, Takashi INOUE, Yasunori IGASAKI
  • Publication number: 20140026757
    Abstract: A vial feed device is equipped with a feed arm, which is positioned between a vial tray and an oven and below either of them and having a feeding housing unit and a cooling housing unit, and a vial up-and-down moving mechanism for placing and removing vials in and from vial tray and oven. Feed arm is rotationally driven by a drive motor to move a feeding housing unit, a cooling housing unit and up-and-down moving mechanism toward vial tray or oven. High-temperature vials in oven are housed in cooling housing unit until cooling time T elapses. After cooling time T elapses, cooling housing unit is moved to a lower part of vial tray by feed arm, to be returned to vial tray by up-and-down moving mechanism.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 30, 2014
    Applicant: SHIMADZU CORPORATION
    Inventors: Takashi INOUE, Takeshi MAJI, Hirotaka NAGANUMA, Shinichi MITSUHASHI, Yoshitaka NODA
  • Patent number: 8635710
    Abstract: Optical information and topographic information of the surface of a sample are measured at a nanometer-order resolution and with high reproducibility without damaging a probe and the sample by combining a nanometer-order cylindrical structure with a nanometer-order microstructure to form a plasmon intensifying near-field probe having a nanometer-order optical resolution and by repeating approach/retreat of the probe to/from each measurement point on the sample at a low contact force.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: January 21, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Toshihiko Nakata, Masahiro Watanabe, Takashi Inoue, Kishio Hidaka, Makoto Okai, Toshiaki Morita, Motoyuki Hirooka
  • Publication number: 20140015019
    Abstract: The reliability of a field effect transistor made of a nitride semiconductor material is improved. An ohmic electrode includes a plurality of unit electrodes isolated to be separated from each other. With this configuration, an on-state current can be prevented from flowing in the unit electrodes in a y-axial direction (negative direction). Further, in the respective unit electrodes, a current density of the on-state current flowing in the y-axial direction (negative direction) can be prevented from increasing. As a result, an electromigration resistance of the ohmic electrode can be improved.
    Type: Application
    Filed: July 9, 2013
    Publication date: January 16, 2014
    Inventors: Yasuhiro OKAMOTO, Takashi INOUE, Tatsuo NAKAYAMA, Ryohei NEGA, Masaaki KANAZAWA, Hironobu MIYAMOTO
  • Publication number: 20130341308
    Abstract: In an aberration-correcting method according to an embodiment of the present invention, in an aberration-correcting method for a laser irradiation device 1 which focuses a laser beam on the inside of a transparent medium 60, aberration of a laser beam is corrected so that a focal point of the laser beam is positioned within a range of aberration occurring inside the medium. This aberration range is not less than n×d and not more than n×d+?s from an incidence plane of the medium 60, provided that the refractive index of the medium 60 is defined as n, a depth from an incidence plane of the medium 60 to the focus of the lens 50 is defined as d, and aberration caused by the medium 60 is defined as ?s.
    Type: Application
    Filed: August 9, 2013
    Publication date: December 26, 2013
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Haruyasu ITO, Naoya MATSUMOTO, Takashi INOUE
  • Patent number: 8610993
    Abstract: A light control device 1 includes a light source 10, a prism 20, a spatial light modulator 30, a drive unit 31, a control unit 32, a lens 41, an aperture 42, and a lens 43. The spatial light modulator 30 is a phase modulating spatial light modulator, includes a plurality of two-dimensionally arrayed pixels, is capable of phase modulation in each of these pixels in a range of 4?, and presents a phase pattern to modulate the phase of light in each of the pixels. This phase pattern is produced by superimposing a blazed grating pattern for light diffraction with a phase modulation range of 2? or less and a phase pattern having a predetermined phase modulation distribution with a phase modulation range of 2? or less.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: December 17, 2013
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Naoya Matsumoto, Taro Ando, Takashi Inoue, Yoshiyuki Ohtake