Patents by Inventor Takashi Kumagai

Takashi Kumagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120019566
    Abstract: An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 26, 2012
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Satoru Ito, Masahiko Moriguchi, Kazuhiro Maekawa, Noboru Itomi, Satoru Kodaira, Junichi Karasawa, Takashi Kumagai, Hisanobu Ishiyama, Takashi Fujise
  • Publication number: 20120007671
    Abstract: An output signal SHS is secondarily amplified by a high-frequency amplifier AMP3 and an output signal SHR is secondarily amplified by an AMP4 for which high-frequency side amplitude reducing means is taken. In this case, the AMP4 has small gain of a high-frequency region and its output SHR-2 is reduced in amplitude. However, a high-frequency noise has a frequency higher than that of a carrier wave SH and the amplitude of a noise NzB becomes smaller. The other output signal SHS is directly amplified by the wideband amplifier AMP3. The width of an SHS-2 and the width of the SHR-2 are adjusted by amplitude adjusting means throughout the whole region and then mutually added by both signals addition amplifying means again so that the amplitude of the output signal SHS is adjusted to the SHR-2, and a predetermined threshold value is set to extract the noises.
    Type: Application
    Filed: August 29, 2008
    Publication date: January 12, 2012
    Inventors: Hideki Kumagai, Takashi Kumagai
  • Patent number: 8081149
    Abstract: An integrated circuit device includes first to Nth circuit blocks (N is an integer of two or more) disposed along the long side of the integrated circuit device. One circuit block of the first to Nth circuit blocks is a logic circuit block, and another circuit block of the first to Nth circuit blocks is a programmable ROM of which at least part of data stored therein can be programmed by a user. The logic circuit block and the programmable ROM block are adjacently disposed along a first direction. At least part of information stored in the programmable ROM block is supplied to the logic circuit block.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: December 20, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Kanji Natori, Takashi Kumagai
  • Patent number: 8066554
    Abstract: A dust box includes: an attachment portion configured to be attached to a dust-discharging nozzle extending from a housing of an electric tool; and a dust-collecting portion connected to the attachment portion and configured to store dust particles to be discharged from the nozzle. The dust-collecting portion mainly consists of a box which is made of synthetic resin and configured to be detachably connected to the attachment portion, and a paper bag received in the box and configured to store the dust particles to be discharged from the nozzle.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: November 29, 2011
    Assignee: Makita Corporation
    Inventors: Yukio Yamashiro, Hirokazu Hagiwara, Yoshifumi Morita, Takashi Kumagai
  • Patent number: 8054710
    Abstract: An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: November 8, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Satoru Ito, Masahiko Moriguchi, Kazuhiro Maekawa, Noboru Itomi, Satoru Kodaira, Junichi Karasawa, Takashi Kumagai, Hisanobu Ishiyama, Takashi Fujise
  • Patent number: 8004204
    Abstract: A series load circuit is a circuit formed by connecting a light-emitting device unit 851 (the first load circuit) and a light-emitting device unit 852 (the second load circuit) in series. A voltage generating circuit 111 generates voltage to be applied to the series load circuit. A current detecting circuit 112 detects electric current flowing through the light-emitting device unit 851. A controlling circuit 114 controls the voltage generating circuit 111 so that the electric current detected by the current detecting circuit 112 becomes a predetermined current value.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: August 23, 2011
    Assignees: Mitsubishi Electric Corporation, Mitsubishi Electric Lighting Corporation
    Inventors: Takafumi Nonaka, Takashi Kumagai, Noriyuki Matsubara, Kazuo Ban, Koichi Saito
  • Patent number: 7986541
    Abstract: An integrated circuit device has a display memory which stores data for at least one frame displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory includes a plurality of RAM blocks, each of the RAM blocks including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit, each of the RAM blocks is disposed along a first direction in which the bitlines extend, each of the memory cells has a short side and a long side, the bitlines are formed along a direction in which the long side of the memory cell extends, and the wordlines are formed along a direction in which the short side of the memory cell extends.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: July 26, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Satoru Kodaira, Noboru Itomi, Shuji Kawaguchi, Takashi Kumagai, Junichi Karasawa, Satoru Ito
  • Publication number: 20110172445
    Abstract: An object of the present invention is to provide a novel antischistosomal agent, and more specifically, to provide a novel drug capable of inhibiting a growth of schistosomes in vivo to prevent development of liver dysfunction due to eggs of the schistosomes in the case of infection with the schistosomes. The novel antischistosomal agent includes as an active ingredient a peroxide derivative. Specifically, the novel antischistosomal agent includes as an active ingredient a peroxide derivative represented by the general formula (I): where C represents an alicyclic hydrocarbon ring group which may be substituted, and n represents an integer of 1 to 6.
    Type: Application
    Filed: June 26, 2009
    Publication date: July 14, 2011
    Applicant: NATIONAL UNIVERSITY CORPORATION OKAYAMA UNIVERSITY
    Inventors: Yusuke Wataya, Hye-Sook Kim, Akiko Hiramoto, Akira Sato, Nobuo Ota, Takashi Kumagai, Rieko Shimogawara, Toshie Taniguchi
  • Publication number: 20110128274
    Abstract: An integrated circuit device includes first and second transistors NTr1 and PTr1 push-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node ND by a charge-pump operation, and a pad PD electrically connected with the connection node ND and electrically connected with a flying capacitor, to which a given voltage is applied at one end, at the other end of the flying capacitor. The pad PD is disposed in an upper layer of at least one of the first and second transistors NTr1 and PTr1 so that the pad PD overlaps part or the entirety of at least one of the first and second transistors NTr1 and PTr1.
    Type: Application
    Filed: February 8, 2011
    Publication date: June 2, 2011
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Takashi Kumagai, Hisanobu Ishiyama, Kazuhiro Maekawa, Satoru ITO, Takashi Fujise, Junichi Karasawa, Satoru Kodaira, Takayuki Saiki, Hiroyuki Takamiya
  • Patent number: 7924833
    Abstract: The present invention relates to a packet transfer unit, which comprises a search key memory that stores a search key for a transfer destination of a packet and verification information generated from the search key, in association with a storage location of transfer information memorized in a transfer information memory, wherein a transfer information acquisition unit searches the search key memory by using the search key generated based on the header information and the verification information generated from the search key, acquires storage location information of the transfer information from the search key memory when a match with the search key and the verification information memorized in the search key memory is found, and acquires the transfer information stored in the transfer information memory based on the acquired storage location information, and wherein a transfer unit transfers the packet based on the acquired transfer information.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: April 12, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Tatsuo Kanetake, Kazuo Sugai, Takashi Kumagai
  • Patent number: 7859928
    Abstract: An integrated circuit device having a display memory which stores data for at least one frame from among image information displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and the wordline control circuit selecting an identical wordline N times (N is an integer larger than one) from among the wordlines in one horizontal scan period of the display panel.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: December 28, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Satoru Kodaira, Noboru Itomi, Shuji Kawaguchi, Takashi Kumagai, Junichi Karasawa, Satoru Ito
  • Patent number: 7782694
    Abstract: An integrated circuit device includes a display memory and a data read control circuit. The data read control circuit controls data reading so that data of pixels corresponding to a plurality of signal lines is read out by N-time reading in one horizontal scan period of a display panel (N is an integer larger than 1). The display memory includes a plurality of sense amplifier cells respectively connected with a plurality of bitlines. L sense amplifier cells (L is an integer larger than 1) respectively connected with the bitlines of L memory cells adjacent in a first direction (wordline direction) in which wordlines extend are disposed along a second direction (bitline direction) in which the bitlines extend.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: August 24, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Satoru Kodaira, Noboru Itomi, Shuji Kawaguchi, Takashi Kumagai, Junichi Karasawa, Satoru Ito, Masahiko Moriguchi, Kazuhiro Maekawa
  • Publication number: 20100194307
    Abstract: A series load circuit is a circuit formed by connecting a light-emitting device unit 851 (the first load circuit) and a light-emitting device unit 852 (the second load circuit) in series. A voltage generating circuit 111 generates voltage to be applied to the series load circuit. A current detecting circuit 112 detects electric current flowing through the light-emitting device unit 851. A controlling circuit 114 controls the voltage generating circuit 111 so that the electric current detected by the current detecting circuit 112 becomes a predetermined current value.
    Type: Application
    Filed: June 15, 2009
    Publication date: August 5, 2010
    Applicants: Mitsubishi Electric Corporation, Mitsubishi Electric Lighting Corporation
    Inventors: Takafumi Nonaka, Takashi Kumagai, Noriyuki Matsubara, Kazuo Ban, Koichi Saito
  • Patent number: 7764278
    Abstract: An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include at least one memory block MB which stores image data, and at least one data driver block DB which drives data lines. The memory block MB and the data driver block DB are disposed adjacent to each other along the first direction D1.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: July 27, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Takashi Kumagai, Hisanobu Ishiyama, Kazuhiro Maekawa, Satoru Ito, Takashi Fujise, Junichi Karasawa, Satoru Kodaira, Katsuhiko Maki
  • Publication number: 20100177540
    Abstract: In a power conversion apparatus that boosts a solar light voltage, converts it to AC and supplies AC power to a load or system, power loss is reduced and efficiency is improved. An inverter unit, in which AC sides of three single-phase inverters receive DC power from respective sources with a voltage ratio of 1:3:9 as respective inputs are connected in series. Gradational output voltage control of an output voltage is carried out using the sum of the respective generated AC voltages. Also, a solar light voltage is boosted by a chopper circuit to generate the highest voltage DC power source. When the solar light voltage exceeds a predetermined voltage, the boosting of the chopper circuit is stopped, thereby reducing power loss due to the boosting.
    Type: Application
    Filed: March 2, 2010
    Publication date: July 15, 2010
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akihiko Iwata, Makoto Seto, Masaki Yamada, Shigeki Harada, Noriyuki Matsubara, Takashi Kumagai
  • Patent number: 7755587
    Abstract: An integrated circuit device includes first to Nth circuit blocks CB1 to CBN disposed along a direction D1 when a direction from a first side which is a short side of the integrated circuit device toward a third side opposite to the first side is a direction D1 and a direction from a second side which is a long side of the integrated circuit device toward a fourth side opposite to the second side is a direction D2. At least one of the circuit blocks on both ends of the circuit blocks CB1 to CBN is a scan driver block for driving a scan line. Or, the scan driver block SB is disposed along the direction D1 on the side of the first to Nth circuit blocks in the direction D2.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: July 13, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Takashi Kumagai, Hisanobu Ishiyama, Kazuhiro Maekawa, Satoru Ito, Takashi Fujise, Junichi Karasawa, Satoru Kodaira
  • Patent number: 7719865
    Abstract: In a power conversion apparatus that boosts a solar light voltage, converts it to AC and supplies AC power to a load or system, power loss is reduced and efficiency is improved. An inverter unit, in which AC sides of three single-phase inverters receive DC power from respective sources with a voltage ratio of 1:3:9 as respective inputs are connected in series. Gradational output voltage control of an output voltage is carried out using the sum of the respective generated AC voltages. Also, a solar light voltage is boosted by a chopper circuit to generate the highest voltage DC power source. When the solar light voltage exceeds a predetermined voltage, the boosting of the chopper circuit is stopped, thereby reducing power loss due to the boosting.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: May 18, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Akihiko Iwata, Makoto Seto, Masaki Yamada, Shigeki Harada, Noriyuki Matsubara, Takashi Kumagai
  • Patent number: 7711698
    Abstract: A communication system includes a first storage section for storing a plurality of pieces of contents information, a second storage section for storing a plurality of pieces of contents information, a control section for accessing the contents information stored in the first storage section and the second storage section based on a single set of management information for managing the contents information stored in the first storage section and the second storage section, a communication section for interconnecting the first storage section, the second storage section and the control section for communication, and an accounting setting section for setting an amount of money to be imposed on a predetermined user in response to use of the first storage section or the second storage section.
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: May 4, 2010
    Assignee: Sony Corporation
    Inventors: Takashi Kumagai, Izuru Tanaka
  • Publication number: 20100073082
    Abstract: Provided is a highly efficient rectifier which can readily replace a two-terminal diode and whose conduction loss is reduced from that of the two-terminal diode. Connected between the source and drain of a MOSFET (2) including a parasitic diode (2a) are: a micro-power converter section (3) for boosting a conduction voltage Vds between the source and drain to a predetermined voltage; and a self-drive control section (4) that operates based on a voltage outputted from the micro-power converter section (3). When the source and drain are conductive with each other, the micro-power converter section (3) generates, from the conduction voltage Vds, a power source voltage for the self-drive control section (4), and the self-drive control section (4) continues drive control of the MOSFET (2).
    Type: Application
    Filed: December 20, 2007
    Publication date: March 25, 2010
    Applicant: Mitsubishi Electric Corporation
    Inventors: Miyuki Takeshita, Akihiko Iwata, Ikuro Suga, Shigeki Harada, Kenichi Kawabata, Takashi Kumagai, Kenji Fujiwara
  • Publication number: 20090298403
    Abstract: A dust box includes: an attachment portion configured to be attached to a dust-discharging nozzle extending from a housing of an electric tool; and a dust-collecting portion connected to the attachment portion and configured to store dust particles to be discharged from the nozzle. The dust-collecting portion mainly consists of a box which is made of synthetic resin and configured to be detachably connected to the attachment portion, and a paper bag received in the box and configured to store the dust particles to be discharged from the nozzle.
    Type: Application
    Filed: April 27, 2009
    Publication date: December 3, 2009
    Applicant: MAKITA CORPORATION
    Inventors: Yukio Yamashiro, Hirokazu Hagiwara, Yoshifumi Morita, Takashi Kumagai