Abstract: A semiconductor device includes a compound semiconductor substrate including a gate region and an active region, a trench provided in a range between the gate region and the active region, a gate insulating film disposed in the trench, a source electrode, and a drain electrode. The gate region includes a first gate region of a p-type being in contact with the gate insulating film, a second gate region of the p-type having a p-type impurity concentration lower than a p-type impurity concentration of the first gate region, a third gate region of an n-type, and a fourth gate region of the p-type. The active region includes a source region of the n-type being in contact with the gate insulating film, a body region of the p-type facing the second gate region via the gate insulating film, and a drain region of the n-type.

Abstract: Disclosed herein is a bipolar transistor capable of improving a current amplification rate while improving voltage resistance. A bipolar transistor is provided with a p-type emitter region, a p-type collector region, an n-type base region located between the emitter region and the collector region, a p-type first embedded region located below the base region, and an n-type region having a lower n-type impurity concentration than the base region, being in contact with the emitter region, the collector region, the base region and the first embedded region, separating the emitter region from the base region and the first embedded region, and separating the collector region from the base region and the first embedded region. A part of the base region projects out toward a collector region side than the first embedded region does.

Abstract: Presented is a bipolar transistor capable of improving a current amplification rate while improving voltage resistance. A bipolar transistor is provided with a p-type emitter region, a p-type collector region, an n-type base region located between the emitter region and the collector region, a p-type first embedded region located below the base region, and an n-type region having a lower n-type impurity concentration than the base region. The base region is provided with a first high-concentration region and a low-concentration region positioned above the first embedded region, and a second high-concentration region positioned on a collector region side than the low-concentration region, wherein the second high-concentration region has a higher n-type impurity concentration than the low-concentration region.

Abstract: A branching structure for connecting a branch harness to a main line harness, includes connection terminals configured to electrically connect branch lines of the branch harness to main lines of the main line harness respectively, a terminal block on which the connection terminals are supported, and fasteners that respectively fasten the connection terminals onto the terminal block. Each of the connection terminals has a belt-shaped wound portion to be wound around a corresponding one of the main lines. The wound portion is fastened by a corresponding one of the fasteners so that both ends of the wound portion come closer to each other and a center portion of the wound portion tightens around the main line so as to be brought into surface contact with a bar conductor of the main line.

Abstract: A semiconductor device may include a semiconductor layer, an insulation gate section, and a first conductivity-type semiconductor region; wherein the semiconductor layer may include a vertical drift region being of a second conductivity type and disposed at the one of main surfaces; a body region being of the first conductivity type, adjoining the vertical drift region, and disposed at the one of main surfaces; and a source region being of the second conductivity type, separated from the vertical drift region by the body region, and disposed at the one of main surfaces, wherein the insulation gate section is opposed to a portion of the body region which separates the vertical drift region and the source region; and the first conductivity-type semiconductor region is opposed to at least a part of a portion of the vertical drift region which is disposed at the one of main surfaces.

Abstract: The switching device includes an electron transport layer; an electron supply layer provided on the electron transport layer and being in contact with the electron transport layer by heterojunction; a source electrode being in contact with the electron supply layer; a drain electrode being in contact with the electron supply layer at a position spaced from the source electrode; and a first gate electrode provided above the electron supply layer, and provided between the source electrode and the drain electrode when viewed in a plan view from above. The first gate electrode is electrically connected above the electron supply layer to the drain electrode. An on-resistance of the switching device is lower than an electric resistance between the first gate electrode and the drain electrode.

Abstract: The switching device includes an electron transport layer; an electron supply layer provided on the electron transport layer and being in contact with the electron transport layer by heterojunction; a source electrode being in contact with the electron supply layer; a drain electrode being in contact with the electron supply layer at a position spaced from the source electrode; and a first gate electrode provided above the electron supply layer, and provided between the source electrode and the drain electrode when viewed in a plan view from above. The first gate electrode is electrically connected above the electron supply layer to the drain electrode. An on-resistance of the switching device is lower than an electric resistance between the first gate electrode and the drain electrode.

Abstract: A hetero-junction semiconductor device includes: a channel layer that includes a first semiconductor; a barrier layer that is provided on the channel layer and includes a semiconductor having a band gap larger than a band gap of the first semiconductor; a source electrode and a drain electrode that are provided on the barrier layer and are ohmic contacted to the barrier layer; a p-type semiconductor layer provided on the barrier layer, the p-type semiconductor layer being provided in a region between the source electrode and the drain electrode on the barrier layer; an n-type semiconductor layer that is provided on the p-type semiconductor layer; and a gate electrode that is joined to the n-type semiconductor layer. A joint interface between the p-type semiconductor layer and the n-type semiconductor layer has a concavo-convex structure.

Abstract: A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer located on the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; a p-type semiconductor layer located on the second nitride semiconductor layer; and a gate electrode located on the p-type semiconductor layer. A first interface and a second interface are located in parallel between the gate electrode and the p-type semiconductor layer. The first interface has a first barrier with respect to holes moving in a direction from the p-type semiconductor layer to the gate electrode. The second interface has a second barrier with respect to the holes moving in a direction from the p-type semiconductor layer to the gate electrode. The second barrier is higher than the first barrier.

Abstract: An insulated gate switching element includes: a semiconductor substrate; a gate insulating film disposed on a surface of the semiconductor substrate; and a gate electrode disposed on the gate insulating film. The semiconductor substrate includes a first semiconductor region, a base region, and a second semiconductor region. The gate electrode faces the base region with the gate insulating film interposed therebetween. A high-resistance region, which is separated from the gate insulating film and has higher resistance to a number of carriers of a first conduction type semiconductor than that of the base region, is disposed in at least one of a first interface which is an interface between the base region and the first semiconductor region and a second interface which is an interface between the base region and the second semiconductor region.

Abstract: A hetero-junction semiconductor device includes: a channel layer that includes a first semiconductor; a barrier layer that is provided on the channel layer and includes a semiconductor having a band gap larger than a band gap of the first semiconductor; a source electrode and a drain electrode that are provided on the barrier layer and are ohmic contacted to the barrier layer; a p-type semiconductor layer provided on the barrier layer, the p-type semiconductor layer being provided in a region between the source electrode and the drain electrode on the barrier layer; an n-type semiconductor layer that is provided on the p-type semiconductor layer; and a gate electrode that is joined to the n-type semiconductor layer. A joint interface between the p-type semiconductor layer and the n-type semiconductor layer has a concavo-convex structure.

Abstract: A semiconductor device is capable of accurately sensing a temperature of a semiconductor element incorporated in a semiconductor substrate. The semiconductor device includes a temperature sensor. The temperature sensor includes a first nitride semiconductor layer of p-type, a first sense electrode, and a second sense electrode. The first sense electrode and the second sense electrode are located to be capable of passing an electric current between the first sense electrode and the second sense electrode through the first nitride semiconductor layer.

Abstract: An insulated gate switching element includes: a semiconductor substrate; a gate insulating film disposed on a surface of the semiconductor substrate; and a gate electrode disposed on the gate insulating film. The semiconductor substrate includes a first semiconductor region, a base region, and a second semiconductor region. The gate electrode faces the base region with the gate insulating film interposed therebetween. A high-resistance region, which is separated from the gate insulating film and has higher resistance to a number of carriers of a first conduction type semiconductor than that of the base region, is disposed in at least one of a first interface which is an interface between the base region and the first semiconductor region and a second interface which is an interface between the base region and the second semiconductor region.

Abstract: A semiconductor substrate includes: a first conduction type first semiconductor region exposed at a first surface; a second conduction type main base region exposed at the first surface at a position adjacent to the first semiconductor region; and a second conduction type surface layer base region which is exposed at the first surface at a position adjacent to the main base region and has a smaller thickness than that of the main base region. A gate electrode is disposed across upper portions of the first semiconductor region, the main base region, and the surface layer base region.

Abstract: A semiconductor device includes a first main electrode; a second main electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of the first conductivity type; a third semiconductor region of a second conductivity type arranged between the first semiconductor region and the second semiconductor region; and a depletion layer suppression region arranged inside of the third semiconductor region and being configured to suppress a spread of a depletion layer extending in the third semiconductor region when a reverse bias voltage is applied between the second semiconductor region and the third semiconductor region. The third semiconductor region includes a shortest region where a distance between a first boundary surface and a second boundary surface is shortest, and the shortest region includes a region where the depletion layer suppression region does not exist between the first boundary surface and the second boundary surface.

Abstract: A Zener diode includes a semiconductor substrate, an anode electrode and a cathode electrode. The semiconductor substrate includes a p-type anode region, an n-type current path region and a drift region. The p-type anode region is connected to the anode electrode. The n-type current path region is in contact with the anode region. The drift region is in contact with the anode region and the current path region. The drift region is of an n type. The drift region has a lower n-type impurity concentration than the current path region. The drift region is connected to the cathode electrode directly or via another n-type region.

Abstract: Presented is a bipolar transistor capable of improving a current amplification rate while improving voltage resistance. A bipolar transistor is provided with a p-type emitter region, a p-type collector region, an n-type base region located between the emitter region and the collector region, a p-type first embedded region located below the base region, and an n-type region having a lower n-type impurity concentration than the base region. The base region is provided with a first high-concentration region and a low-concentration region positioned above the first embedded region, and a second high-concentration region positioned on a collector region side than the low-concentration region, wherein the second high-concentration region has a higher n-type impurity concentration than the low-concentration region.

Abstract: A semiconductor device includes a first main electrode; a second main electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of the first conductivity type; a third semiconductor region of a second conductivity type arranged between the first semiconductor region and the second semiconductor region; and a depletion layer suppression region arranged inside of the third semiconductor region and being configured to suppress a spread of a depletion layer extending in the third semiconductor region when a reverse bias voltage is applied between the second semiconductor region and the third semiconductor region. The third semiconductor region includes a shortest region where a distance between a first boundary surface and a second boundary surface is shortest, and the shortest region includes a region where the depletion layer suppression region does not exist between the first boundary surface and the second boundary surface.

Abstract: Disclosed herein is a bipolar transistor capable of improving a current amplification rate while improving voltage resistance. A bipolar transistor is provided with a p-type emitter region, a p-type collector region, an n-type base region located between the emitter region and the collector region, a p-type first embedded region located below the base region, and an n-type region having a lower n-type impurity concentration than the base region, being in contact with the emitter region, the collector region, the base region and the first embedded region, separating the emitter region from the base region and the first embedded region, and separating the collector region from the base region and the first embedded region. A part of the base region projects out toward a collector region side than the first embedded region does.

Abstract: A semiconductor device disclosed herein is provided with: a source electrode; a gate electrode; a drain electrode; a first region of a first conductivity type formed in a range exposed at an upper surface of the semiconductor substrate a second region of a second conductivity type; a third region of the first conductivity type; and a fourth region of the first conductivity type. The fourth region includes: a first drift region formed in a range exposed at the upper surface; a second drift region having a first conductivity type impurity concentration higher than that of the first drift region, and adjacent to the first drift region; and a low concentration drift region having a first conductivity type impurity concentration lower than that of the first drift region. The first drift region is projected to a second region side than the second drift region.