Patents by Inventor Takashi Udagawa

Takashi Udagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6462361
    Abstract: A GaInP epitaxial stacking structure and fabrication method thereof, and a FET transistor using this structure are provided wherein, stacked upon a GaAs single-crystal substrate are at least a buffer layer, a GaZIn1−ZAs (0<Z≦1) channel layer, and a GaYIn1−YP (0<Y≦1) electron-supply layer joined to the channel layer, wherein the GaInP epitaxial stacking structure includes a region within the electron-supply layer wherein the gallium composition ratio (Y) decreases from the side of the junction interface with the channel layer toward the opposite side.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: October 8, 2002
    Assignee: Showa Denko K.K.
    Inventors: Takashi Udagawa, Masahiro Kimura, Akira Kasahara, Taichi Okano
  • Publication number: 20020113235
    Abstract: A Group-III nitride semiconductor light-emitting diode having an electrically conducting silicon (Si) single crystal substrate having on an upper surface thereof at least a light-emitting part having a pn-heterojunction structure composed of a Group-III nitride semiconductor, which light-emitting part is stacked via an intermediate layer composed of a metal or a semiconductor, the single crystal substrate having a back surface electrode on a back surface thereof, a surface electrode on an upper surface of the light-emitting part and a perforated part formed by eliminating the Si single crystal substrate in a region exclusive of the back surface electrode on the back surface of the single crystal substrate and a method of manufacturing thereof are disclosed.
    Type: Application
    Filed: February 19, 2002
    Publication date: August 22, 2002
    Applicant: SHOWA DENKO K.K.
    Inventor: Takashi Udagawa
  • Patent number: 6403987
    Abstract: An electrode for a light-emitting semiconductor device includes a light-permeable electrode formed to come into contact with the surface of the semiconductor, and a wire-bonding electrode that is in electrical contact with the light-permeable electrode and is formed to come into partial contact with the surface of the semiconductor with at least a region in contact with the semiconductor having a higher contact resistance per unit area with respect to the semiconductor than a region of the light-permeable electrode in contact with the semiconductor.
    Type: Grant
    Filed: October 24, 2000
    Date of Patent: June 11, 2002
    Assignee: Showa Denko K.K.
    Inventors: Hisayuki Miki, Takashi Udagawa, Noritaka Muraki, Mineo Okuyama
  • Publication number: 20020066911
    Abstract: A GaInP stacked layer structure 1 having a GaAs single crystal substrate 10 having stacked on the surface thereof at least a buffer layer 11, an electron channel layer 12 composed of GaXIn1-XAs (0≦X≦1), a spacer layer 13 composed of GaInP and an electron supply layer 14 composed of GaInP is disclosed. The electron channel layer 12 contains a compositional gradient region imparted with a gradient by increasing the indium composition ratio (1-X) in the direction of the layer thickness increasing toward the junction interface 12b with the electron supply layer 14 side.
    Type: Application
    Filed: December 5, 2001
    Publication date: June 6, 2002
    Applicant: SHOWA DENKO K.K.
    Inventor: Takashi Udagawa
  • Patent number: 6346719
    Abstract: An object of the present invention is to provide a high brightness n-side-up type AlGaInP light-emitting device with a simple structure. An n-type upper cladding layer is constructed by superimposing three n-type AlGaInP layers with different electron concentrations. The relationship between the electron concentrations of the three n-type AlGaInP layers is n3>n1>n2.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: February 12, 2002
    Assignee: Showa Denko Kabushiki Kaisha
    Inventors: Takashi Udagawa, Toshiki Yoshiuji, Ryouichi Takeuchi
  • Publication number: 20020000563
    Abstract: The present invention solves the problem of conventional group-III nitride semiconductor LED in that, since the LED driving current is supplied only from a pad electrode serving also as an ohmic electrode, the driving current cannot diffuse over a wide range of the light-emitting region and a group-III nitride semiconductor LED having high light emission intensity cannot be successfully provided. A group-III nitride semiconductor LED having high light emission intensity, which is fabricated using a stacked layer structure obtained by providing a surface ohmic electrode, a window layer including an electrically conducting transparent oxide crystal layer and a pad electrode on an electrically conducting substrate through a boron phosphide (BP)-based buffer layer to allow the driving current to diffuse over a wide range of the light-emitting region is provided.
    Type: Application
    Filed: June 18, 2001
    Publication date: January 3, 2002
    Applicant: SHOWA DENKO K.K.
    Inventor: Takashi Udagawa
  • Patent number: 6335219
    Abstract: A nitride semiconductor light emitting device which uses as a light emitting layer an indium-containing group-III nitride semiconductor layer of a multi-phase structure composed of a main phase and sub-phases having different indium contents is characterized in that the sub-phases are mainly formed of crystal whose boundary with the main phase is surrounded by a strained layer.
    Type: Grant
    Filed: July 24, 2000
    Date of Patent: January 1, 2002
    Assignee: Showa Denko K.K.
    Inventor: Takashi Udagawa
  • Publication number: 20010054717
    Abstract: A high emission intensity group-III nitride semiconductor light-emitting device obtained by eliminating crystal lattice mismatch with substrate crystal and using a gallium nitride phosphide-based light emitting structure having excellent crystallinity. A gallium nitride phosphide-based multilayer light-emitting structure is formed on a substrate via a boron phosphide (BP)-based buffer layer. The boron phosphide-based buffer layer is preferably grown at a low temperature and rendered amorphous so as to eliminate the lattice mismatch with the substrate crystal. After the amorphous buffer layer is formed, it is gradually converted into a crystalline layer to fabricate a light-emitting device while keeping the lattice match with the gallium nitride phosphide-based light-emitting part.
    Type: Application
    Filed: June 22, 2001
    Publication date: December 27, 2001
    Applicant: SHOWA DENKO K.K
    Inventor: Takashi Udagawa
  • Patent number: 6326223
    Abstract: An electrode for a light-emitting semiconductor device includes a light-permeable electrode formed to come into contact with the surface of the semiconductor, and a wire-bonding electrode that is in electrical contact with the light-permeable electrode and is formed to come into partial contact with the surface of the semiconductor with at least a region in contact with the semiconductor having a higher contact resistance per unit area with respect to the semiconductor than a region of the light-permeable electrode in contact with the semiconductor.
    Type: Grant
    Filed: October 24, 2000
    Date of Patent: December 4, 2001
    Assignee: Showa Denko K.K.
    Inventors: Hisayuki Miki, Takashi Udagawa, Noritaka Muraki, Mineo Okuyama
  • Publication number: 20010036678
    Abstract: The present invention provides an n-side-up type group III nitride semiconductor light-emitting device fabricated from an epitaxial wafer having group III nitride semiconductor crystal layers with different crystal structures, i.e., cubic and hexagonal systems. A buffer layer of a boron phosphide (BP) based material, a cubic p-type single crystal layer of a BP based material, a cubic p-type group III nitride semiconductor crystal layer, and a hexagonal n-type group III nitride semiconductor crystal layer are successively formed on a substrate of a p-type conduction Si single crystal. The temperatures for the formation of the above-mentioned buffer layer, cubic p-type group III nitride semiconductor crystal layer, and a hexagonal n-type group III nitride semiconductor crystal layer are desirably in preferred ranges.
    Type: Application
    Filed: April 20, 2001
    Publication date: November 1, 2001
    Inventor: Takashi Udagawa
  • Publication number: 20010035530
    Abstract: An object of the present invention is to reduce variance in the flow rates of source gasses and inconsistency in the mixing ratio of the source gasses when the flow paths of the source gasses are switched in a vent/run-type piping system of a vapor deposition apparatus. In a vapor deposition apparatus, a run line for mixing one or more sources with a carrier gas and for supplying the resultant gas to a vapor deposition region; a vent line for allowing the sources to detour away from the vapor deposition region and exhausting the sources; and a mechanism for switching the paths of the sources from the vapor deposition region to the vent line are provided. The paths of the sources are switched from the vent line to the vapor deposition region when the mixing ratio of the sources becomes consistent in the run line.
    Type: Application
    Filed: April 26, 2001
    Publication date: November 1, 2001
    Inventor: Takashi Udagawa
  • Patent number: 6268618
    Abstract: An electrode for a light-emitting semiconductor device includes a light-permeable electrode formed to come into contact with the surface of the semiconductor, and a wire-bonding electrode that is in electrical contact with the light-permeable electrode and is formed to come into partial contact with the surface of the semiconductor with at least a region in contact with the semiconductor having a higher contact resistance per unit area with respect to the semiconductor than a region of the light-permeable electrode in contact with the semiconductor.
    Type: Grant
    Filed: May 7, 1998
    Date of Patent: July 31, 2001
    Assignee: Showa Denko K.K.
    Inventors: Hisayuki Miki, Takashi Udagawa, Noritaka Muraki, Mineo Okuyama
  • Patent number: 6194744
    Abstract: A method of growing a group III nitride semiconductor crystal layer includes a step of growing a first buffer layer composed of boron phosphide on a silicon single crystal substrate by a vapor phase growth method at a temperature of not lower than 200° C. and not higher than 700° C., a step of growing a second buffer layer composed of boron phosphide on the first buffer layer by a vapor phase growth method at a temperature of not lower than 750° C. and not higher than 1200° C., and a step of growing a crystal layer composed of group III nitride semiconductor crystal represented by general formula AlpGaqInrN (where 0≦p≦1, 0≦q≦1, 0≦r≦1, p+q+r=1) on the second buffer layer by a vapor phase growth method. A semiconductor device incorporating the group III nitride semiconductor crystal layer is provided.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: February 27, 2001
    Assignee: Showa Denko Kabushiki Kaisha
    Inventors: Takashi Udagawa, Kazutaka Terashima, Suzuka Nishimura, Takuji Tsuzaki
  • Patent number: 6153894
    Abstract: Light-emitting device with excellent emission intensity is difficult to obtain when gallium indium nitride with high indium composition ratio and poor crystallinity is employed as active layer for group-III nitride light-emitting device to emit a comparatively long wavelength light. The invention provides a light-emitting layer on a super lattice structure as a base layer, and crystallinity of the light-emitting layer is then improved. Furthermore, abruptness of a crystal composition at an interface of the light-emitting layer and an upper junction layer is achieved, thus forming a bending portion of a band structure expedient for allowing the emitting-layer to emit a light with a long wavelength.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: November 28, 2000
    Assignee: Showa Denko Kabushiki Kaisha
    Inventor: Takashi Udagawa
  • Patent number: 6147363
    Abstract: A nitride semiconductor light emitting device which uses as a light emitting layer an indium-containing group-III nitride semiconductor layer of a multi-phase structure composed of a main phase and sub-phases having different indium contents is characterized in that the sub-phases are mainly formed of crystal whose boundary with the main phase is surrounded by a strained layer.
    Type: Grant
    Filed: December 22, 1998
    Date of Patent: November 14, 2000
    Assignee: Showa Denko K.K.
    Inventor: Takashi Udagawa
  • Patent number: 6110757
    Abstract: A method of forming an epitaxial wafer for a light-emitting device by sequentially growing a lower cladding layer of Al.sub..alpha. Ga.sub..beta. N (0.ltoreq..alpha., .beta..ltoreq.1, .alpha.+.beta.=1), an AlGaInN active layer, and an upper cladding layer of Al.sub..alpha. Ga.sub..beta. N (0.ltoreq..alpha., .beta..ltoreq.1, .alpha.+.beta.=1) on a single-crystal substrate, wherein the AlGaInN active layer is formed by epitaxially growing an active layer of Al.sub.a Ga.sub.b In.sub.c N (wherein 0.ltoreq.a, b, c.ltoreq.1, a+b+c=1) on the lower cladding layer at a temperature of from 650.degree. C. to 950.degree. C., elevating the temperature of the active layer at a rate of not less than 30.degree. C./min until reaching a temperature range of from more than 950.degree. C. to not more than 1200.degree. C., and when the prescribed temperature is reached, primarily cooling the resultant layer to 950.degree. C. within 60 minutes at not less than 20.degree. C.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: August 29, 2000
    Assignee: Showa Denko K. K.
    Inventor: Takashi Udagawa
  • Patent number: 6069021
    Abstract: A method of growing a group III nitride semiconductor crystal layer includes a step of growing a first buffer layer composed of boron phosphide on a silicon single crystal substrate by a vapor phase growth method at a temperature of not lower than 200.degree. C. and not higher than 700.degree. C., a step of growing a second buffer layer composed of boron phosphide on the first buffer layer by a vapor phase growth method at a temperature of not lower than 750.degree. C. and not higher than 1200.degree. C., and a step of growing a crystal layer composed of group III nitride semiconductor crystal represented by general formula Al.sub.p Ga.sub.q In.sub.r N (where 0.ltoreq.p.ltoreq.1, 0.ltoreq.q.ltoreq.1, 0.ltoreq.r.ltoreq.1, p+q+r=1) on the second buffer layer by a vapor phase growth method. A semiconductor device incorporating the group III nitride semiconductor crystal layer is provided.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: May 30, 2000
    Assignee: Showa Denko K.K.
    Inventors: Kazutaka Terashima, Suzuka Nishimura, Takuji Tsuzaki, Takashi Udagawa
  • Patent number: 5886367
    Abstract: An epitaxial wafer for a light-emitting device has a double hetero-structure and includes a single-crystal substrate, a lower cladding layer of AlGaN grown on the substrate, an active layer grown on the lower cladding layer, the active layer having a two-phase structure comprised of a matrix of Al.sub.x Ga.sub.y In.sub.z N and crystallets of Al.sub.a Ga.sub.b In.sub.c N, and an upper cladding layer of AlGaN grown on the active layer.
    Type: Grant
    Filed: August 6, 1997
    Date of Patent: March 23, 1999
    Assignee: Showa Denko K.K.
    Inventor: Takashi Udagawa
  • Patent number: 5011733
    Abstract: A process for coating a metallic substrate, characterized by applying on a metallic substrate a electrocoating paint, applying thereon a barrier coat comprising a film-forming thermoplastic resin other than a modified polyolefin resin and capable of forming a barrier coat film having a static glass transition temperature of 0.degree. to -75.degree. C., optionally applying on said barrier coat an intermediate coating paint and then applying thereon a top coating paint.
    Type: Grant
    Filed: January 9, 1989
    Date of Patent: April 30, 1991
    Assignee: Kansai Paint Co., Ltd.
    Inventors: Tadayoshi Hiraki, Osamu Iwase, Hirosi Oosumimoto, Shinji Sugiura, Ichiro Tabushi, Masafumi Kume, Takashi Udagawa, Komaharu Matsui, Yasuhiro Fujii
  • Patent number: 4983454
    Abstract: A process for coating a metallic substrate, characterized by applying on a metallic substrate an electrocoating paint, applying thereon a barrier coat comprising a film-forming thermoplastic resin other than a modified polyolefin resin and capable of forming a barrier coat film having a static glass transition temperature of 0.degree. to -75.degree. C., optionally applying on said barrier coat an intermediate coating paint and then applying thereon a top coating paint.
    Type: Grant
    Filed: January 9, 1989
    Date of Patent: January 8, 1991
    Assignee: Kansai Paint Co., Ltd.
    Inventors: Tadayoshi Hiraki, Osamu Iwase, Hirosi Oosumimoto, Shinji Sugiura, Ichiro Tabushi, Masafumi Kume, Takashi Udagawa, Komaharu Matsui, Yasuhiro Fujii