Patents by Inventor Takashi Yamauchi

Takashi Yamauchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100271569
    Abstract: A liquid crystal display device which includes a backlight device provided with an LED, and a color filter having colored layers of plural colors including a green layer, wherein the green layer of the color filter contains brominated zinc phthalocyanine green pigment and a dielectric loss tangent of the green layer at a driving frequency of a liquid crystal display device is confined to not more than 0.02.
    Type: Application
    Filed: July 7, 2010
    Publication date: October 28, 2010
    Applicant: TOPPAN PRINTING CO., LTD.
    Inventors: Satoshi Ohkuma, Atsuko Kamada, Yoshiko Ishimaru, Kenji Muneuchi, Hidesato Hagiwara, Takashi Yamauchi, Noriko Asahi
  • Patent number: 7807538
    Abstract: A metal insulator semiconductor field effect transistor (MISFET) having a strained channel region is disclosed. Also disclosed is a method of fabricating a semiconductor device having a low-resistance junction interface. This fabrication method includes the step of forming a gate electrode above a silicon substrate with a gate insulator film being sandwiched therebetween. Then, form a pair of heavily-doped p (p+) type diffusion layers in or on the substrate surface at both sides of the gate electrode to a concentration of 5×1019 atoms/cm3 or more and yet less than or equal to 1×1021 atoms/cm3. Next, silicidize the p+-type layers by reaction with a metal in the state that each layer is applied a compressive strain.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: October 5, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yamauchi, Atsuhiro Kinoshita, Yoshinori Tsuchiya, Junji Koga
  • Patent number: 7754363
    Abstract: The invention provides a method for inspecting a fuel cell that can simply inspect fuel cell characteristics. The method is an inspecting method for a direct methanol fuel cell generator comprising an anode electrode including an node catalyst layer, a cathode electrode including a cathode catalyst layer, and N pieces of cells having an electrolyte disposed between the anode electrode and the cathode electrode, for power generation by feeding an aqueous methanol solution to the anode electrode and an oxidant gas to the cathode electrode. The fuel cell generator is inspected by measuring voltage changes of the voltage V of one electromotive unit caused by generating a current density change ?I or ??I (mA/cm2) satisfying the condition of 0.2??I?5 in a finite current density I (mA/cm2) loaded on the plural electromotive units arbitrarily connected in series in the fuel cell generator under power generation during a time interval ?t (sec) satisfying the condition of 10?5??t?0.5.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: July 13, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Takashita, Takashi Yamauchi, Yoshihiko Nakano
  • Patent number: 7750068
    Abstract: A colored composition for color filter contains a pigment carrier made of a transparent resin, a precursor thereof, or a mixture thereof, an organic pigment, and a pigment-dispersing agent containing a quinoline derivative having a formula as described in the specification or an amine or metal salt. The color filter contains filter segments formed with the color composition.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: July 6, 2010
    Assignee: Toppan Printing Co., Ltd.
    Inventors: Atsushi Nishida, Toru Omura, Takashi Yamauchi, Takeshi Itoi
  • Publication number: 20100051906
    Abstract: A semiconductor device for correcting an input signal and outputting a corrected signal are provided. The semiconductor device includes a semiconductor layer, a plurality of first conductors formed on one of faces of the semiconductor layer and serving as input terminals to which a signal is input, second conductors of the number larger than that of the first conductors at density higher than that of the first conductors, formed on the other face of the semiconductor layer, a high impurity concentration region provided on the semiconductor layer side of an interface between the second conductor and the semiconductor layer, an insulating layer formed on the other face, and a plurality of third conductors formed on the insulating layer and serving as output terminals for outputting the processed signal.
    Type: Application
    Filed: August 27, 2009
    Publication date: March 4, 2010
    Inventors: Takashi Yamauchi, Yoshifumi Nishi, Hiroto Honda, Kei Masunishi, Shinji Murai, Masumi Saitoh
  • Publication number: 20100044932
    Abstract: Continuous annealing equipment contains: a heating zone, a soaking zone, and a rapid cooling zone, the rapid cooling zone having gas jet cooling equipment and is provided with at least one pair of seal rolls at each of an inlet and an outlet thereof and bridle roll units each composed of two or more bridle rolls in front of and behind itself; the bridle roll unit behind the rapid cooling zone having two or more heating rolls each having an induction heater thereinside; and the heating roll having a winding angle of 100° or more per heating roll and 380° or more in total of all the heating rolls.
    Type: Application
    Filed: February 14, 2008
    Publication date: February 25, 2010
    Applicant: JFE STEEL CORPORATION
    Inventors: Takahiro Sugano, Eiko Yasuhara, Takashi Yamauchi
  • Patent number: 7642604
    Abstract: A semiconductor device having an electrode with reduced electrical contact resistance even where either electrons or holes are majority carriers is disclosed. This device has an n-type diffusion layer and a p-type diffusion layer in a top surface of a semiconductor substrate. The device also has first and second metal wires patterned to overlie the n-type and p-type diffusion layers, respectively, with a dielectric layer interposed therebetween, a first contact electrode for electrical connection between the n-type diffusion layer and the first metal wire, and a second contact electrode for connection between the p-type diffusion layer and the second metal wire. The first contact electrode's portion in contact with the n-type diffusion layer and the second contact electrode's portion contacted with the p-type diffusion layer are each formed of a first conductor that contains a metal and a second conductor containing a rare earth metal.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: January 5, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshifumi Nishi, Takashi Yamauchi, Yoshinori Tsuchiya, Junji Koga
  • Publication number: 20090152652
    Abstract: Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed on the surface of the semiconductor substrate by making the first metal and the semiconductor substrate react each other by a first heat treatment. Ions having a mass equal to or larger than atomic weight of Si are implanted into the metal semiconductor compound layer. A second metal is deposited on the metal semiconductor compound layer. An interface layer is formed by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment.
    Type: Application
    Filed: November 26, 2008
    Publication date: June 18, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshifumi NISHI, Yoshinori Tsuchiya, Takashi Yamauchi, Junji Koga
  • Patent number: 7544434
    Abstract: A direct liquid fuel cell power generating device of the invention comprise an anode electrode, a cathode electrode, an electrolyte membrane held by the anode electrode and the cathode electrode, an anode Passage for passing a fuel, a cathode passage for passing an oxidizer, a fuel container connected to the feed port of the anode passage, and a cathode recovery container connected to the discharge port of the cathode passage for collecting the fuel supplied to an electromotive force section, an unreacted oxidizer, an a product of battery reaction, the device further comprising at least a mechanism for achieving gas-liquid contact by making contact between the substance discharged from the cathode discharge port and water existing in the cathode recovery container, and a mechanism for feeding the aqueous solution collected in the cathode recovery container into the fuel container.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: June 9, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yamauchi, Masahiro Takashita, Yoshihiko Nakano, Yasuhiro Goto
  • Publication number: 20090134388
    Abstract: A semiconductor device having a metal insulator semiconductor field effect transistor (MISFET) with interface resistance-reduced source/drain electrodes is disclosed. This device includes a p-type MISFET formed on a semiconductor substrate. The p-MISFET has a channel region in the substrate, a gate insulating film on the channel region, a gate electrode on the gate insulating film, and a pair of laterally spaced-apart source and drain electrodes on both sides of the channel region. These source/drain electrodes are each formed of a nickel (Ni)-containing silicide layer. The p-MISFET further includes an interface layer which is formed on the substrate side of an interface between the substrate and each source/drain electrode. This interface layer contains magnesium (Mg), calcium (Ca) or barium (Ba) therein. A fabrication method of the semiconductor device is also disclosed.
    Type: Application
    Filed: September 3, 2008
    Publication date: May 28, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi YAMAUCHI, Yoshifumi Nishi, Yoshinori Tsuchiya, Junji Koga, Koichi Kato
  • Publication number: 20090008726
    Abstract: A method of manufacturing a semiconductor device reducing interface resistance of n-type and p-type MISFETs are provided. According to the method, a gate dielectric film and a gate electrode of the n-type MISFET are formed on a first semiconductor region, a gate dielectric film and a gate electrode of the p-type MISFET are formed on a second semiconductor region, an n-type diffusion layer is formed by ion implantation of As into the first semiconductor region, a first silicide layer is formed by first heat treatment after a first metal containing Ni is deposited on the n-type diffusion layer, the first silicide layer is made thicker by second heat treatment after a second metal containing Ni is deposited on the first silicide layer and second semiconductor region, and third heat treatment is provided after formation of a second silicide layer and ion implantation of B or Mg into the second silicide layer.
    Type: Application
    Filed: March 20, 2008
    Publication date: January 8, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi Yamauchi, Yoshifumi Nishi, Atsuhiro Kinoshita, Yoshinori Tsuchiya, Junji Koga, Koichi Kato
  • Publication number: 20090008727
    Abstract: It is made possible to reduce the interface resistance at the interface between the nickel silicide film and the silicon. A semiconductor manufacturing method includes: forming an impurity region on a silicon substrate, with impurities being introduced into the impurity region; depositing a Ni layer so as to cover the impurity region; changing the surface of the impurity region into a NiSi2 layer through annealing; forming a Ni layer on the NiSi2 layer; and silicidating the NiSi2 layer through annealing.
    Type: Application
    Filed: September 11, 2008
    Publication date: January 8, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi YAMAUCHI, Atsuhiro Kinoshita, Yoshinori Tsuchiya, Junji Koga, Koichi Kato, Nobutoshi Aoki, Kazuya Ohuchi
  • Patent number: 7456096
    Abstract: It is made possible to reduce the interface resistance at the interface between the nickel silicide film and the silicon. A semiconductor manufacturing method includes: forming an impurity region on a silicon substrate, with impurities being introduced into the impurity region; depositing a Ni layer so as to cover the impurity region; changing the surface of the impurity region into a NiSi2 layer through annealing; forming a Ni layer on the NiSi2 layer; and silicidating the NiSi2 layer through annealing.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: November 25, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yamauchi, Atsuhiro Kinoshita, Yoshinori Tsuchiya, Junji Koga, Koichi Kato, Nobutoshi Aoki, Kazuya Ohuchi
  • Publication number: 20080230804
    Abstract: A semiconductor device having an electrode with reduced electrical contact resistance even where either electrons or holes are majority carriers is disclosed. This device has an n-type diffusion layer and a p-type diffusion layer in a top surface of a semiconductor substrate. The device also has first and second metal wires patterned to overlie the n-type and p-type diffusion layers, respectively, with a dielectric layer interposed therebetween, a first contact electrode for electrical connection between the n-type diffusion layer and the first metal wire, and a second contact electrode for connection between the p-type diffusion layer and the second metal wire. The first contact electrode's portion in contact with the n-type diffusion layer and the second contact electrode's portion contacted with the p-type diffusion layer are each formed of a first conductor that contains a metal and a second conductor containing a rare earth metal.
    Type: Application
    Filed: February 25, 2008
    Publication date: September 25, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshifumi Nishi, Takashi Yamauchi, Yoshinori Tsuchiya, Junji Koga
  • Publication number: 20080179752
    Abstract: A metal insulator semiconductor field effect transistor (MISFET) having a strained channel region is disclosed. Also disclosed is a method of fabricating a semiconductor device having a low-resistance junction interface. This fabrication method includes the step of forming a gate electrode above a silicon substrate with a gate insulator film being sandwiched therebetween. Then, form a pair of heavily-doped p (p+) type diffusion layers in or on the substrate surface at both sides of the gate electrode to a concentration of 5×1019 atoms/cm3 or more and yet less than or equal to 1×1021 atoms/cm3. Next, silicidize the p+-type layers by reaction with a metal in the state that each layer is applied a compressive strain.
    Type: Application
    Filed: September 11, 2007
    Publication date: July 31, 2008
    Inventors: Takashi Yamauchi, Atsuhiro Kinoshita, Yoshinori Tsuchiya, Junji Koga
  • Publication number: 20080107955
    Abstract: A direct type fuel cell power generator comprises an anode electrode including an anode catalyst layer, a cathode electrode including a cathode catalyst layer, a fuel container comprising at least two electromotive portion units, each of which comprises an electrolyte film disposed between the anode electrode and the cathode electrode, the fuel container housing a fuel therein, and a fuel flow path to supply a fuel in the electromotive portion unit. In the power generator, the fuel flow path has a flow path which produces flow-back again from the fuel container to the first electromotive portion unit via the first electromotive portion unit and the second electromotive portion unit, and which is not branched during the flow-back.
    Type: Application
    Filed: January 8, 2008
    Publication date: May 8, 2008
    Inventors: Masato Akita, Takashi Yamauchi, Masahiro Takashita, Eiichi Sakaue, Kei Matsuoka
  • Patent number: 7351486
    Abstract: A direct type fuel cell power generator comprises an anode electrode including an anode catalyst layer, a cathode electrode including a cathode catalyst layer, a fuel container comprising at least two electromotive portion units, each of which comprises an electrolyte film disposed between the anode electrode and the cathode electrode, the fuel container housing a fuel therein, and a fuel flow path to supply a fuel in the electromotive portion unit. In the power generator, the fuel flow path has a flow path which produces flow-back again from the fuel container to the first electromotive portion unit via the first electromotive portion unit and the second electromotive portion unit, and which is not branched during the flow-back.
    Type: Grant
    Filed: November 28, 2003
    Date of Patent: April 1, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masato Akita, Takashi Yamauchi, Masahiro Takashita, Eiichi Sakaue, Kei Matsuoka
  • Patent number: 7348591
    Abstract: A switch element includes a substrate; a plurality of carbon nanotubes provided upright on the substrate; magnetic particles arranged at tip ends of the carbon nanotubes respectively; and a plurality of conductive layers formed between base ends of the carbon nanotubes and the substrate. A switching operation of the switching element is performed in such a manner that the carbon nanotubes or the magnetic particles are brought into contact with each other according to an electrical potential between the conductive layers, and the carbon nanotubes are separated from each other when an electrical current flows through the carbon nanotubes with the carbon nanotubes or the magnetic particles brought into contact with each other.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: March 25, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yamauchi, Chika Tanaka, Hideyuki Sugiyama, Atsuhiro Kinoshita, Junji Koga, Yuichi Motoi, Yoshihiko Nakano, Seiichi Suenaga
  • Publication number: 20070298558
    Abstract: A semiconductor device includes a first semiconductor region of first type conductivity with a channel region being formed therein, a gate electrode insulatively formed above the channel region, a layer of SixGe1-x (0<x<1) on both sides of the channel region, a pair of second semiconductor regions of second type conductivity as formed on the SixGe1-x layer to have a controlled impurity concentration ranging from 1021 to 1022 atoms/cm3, and a nickel-containing silicide layer above the second semiconductor regions. A fabrication method of the semiconductor device is also disclosed.
    Type: Application
    Filed: April 23, 2007
    Publication date: December 27, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takashi YAMAUCHI, Atsuhiro Kinoshita, Yoshinori Tsuchiya, Junji Koga
  • Publication number: 20070291412
    Abstract: An opening-closing mechanism for a record medium is arranged to include a moving body moves, on which an inserting slot and a revolving door are provided; a supporting means for causing the revolving door to support by the moving body in openable and closeable manner in the form of opening in; a movement transmission means for enabling an opening and closing operation of the revolving door on condition of the movement of the moving body; and a concave space movably receives therein the moving body.
    Type: Application
    Filed: November 17, 2005
    Publication date: December 20, 2007
    Inventors: Hiroyuki Yabashi, Noboru Yamaguchi, Takashi Yamauchi