Patents by Inventor Takeshi Kawabata

Takeshi Kawabata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8890335
    Abstract: A semiconductor device includes: on an upper surface of a second semiconductor chip on a circuit board, a ring dam section formed at an outer circumference of a mounting region above which a first semiconductor chip is mounted; and an interconnect extending from the dam section to a center section of the first semiconductor chip or the second semiconductor chip in a region in which the first semiconductor chip faces the second semiconductor chip. The interconnect is electrically connected to a connection terminal on a circuit formation surface of the first or second semiconductor chip at the center section of the first or second semiconductor chip. The dam section and the interconnect are power supply interconnects or ground interconnects.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: November 18, 2014
    Assignee: Panasonic Corporation
    Inventors: Kenji Yokoyama, Takeshi Kawabata
  • Publication number: 20140327157
    Abstract: A lamination structure includes a first semiconductor chip and a second semiconductor chip stacked via a bonding section so that a rear surface of the first semiconductor chip faces the main surface of the second semiconductor chip. At least a part of a side surface of the first semiconductor chip are covered with a first resin, a distribution layer is formed on the plane formed of the main surface of the first semiconductor chip and a surface of the first resin. At least part of electrodes existing in the main surface of the second semiconductor chip is electrically connected to at least part of first external electrodes formed on the distribution layer via the penetration electrodes that penetrate the first semiconductor chip.
    Type: Application
    Filed: July 16, 2014
    Publication date: November 6, 2014
    Inventors: NOBUO AOI, MASARU SASAGO, YOSHIHIRO MORI, TAKESHI KAWABATA, TAKASHI YUI, TOSHIO FUJII
  • Publication number: 20140272692
    Abstract: There is provided an actinic ray-sensitive or radiation-sensitive composition comprising (P) a compound having a phenolic hydroxyl group and a group formed by substituting for the hydrogen atom in a phenolic hydroxyl group by a group represented by the specific formula, a resist film formed using the specific actinic ray-sensitive or radiation-sensitive composition, a pattern forming method containing steps of exposing and developing the resist film, a manufacturing method of an electronic device, containing the pattern forming method, and an electronic device manufactured by the specific manufacturing method of an electronic device.
    Type: Application
    Filed: May 29, 2014
    Publication date: September 18, 2014
    Applicant: FUJIFILM CORPORATION
    Inventors: Natsumi YOKOKAWA, Takeshi KAWABATA, Hiroo TAKIZAWA, Hideaki TSUBAKI, Shuji HIRANO
  • Patent number: 8808961
    Abstract: An embodiment of the composition contains any of compounds of the formula A-LG in which A represents any of residues of general formula (A-1) below and LG represents any of groups that are cleaved to generate acids of the formula A-H when acted on by an acid. The composition further contains at least one of a compound that generates an acid when exposed to actinic rays or radiation and a compound that generates an acid when heated.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: August 19, 2014
    Assignee: FUJIFILM Corporation
    Inventors: Tomotaka Tsuchimura, Takeshi Kawabata, Takayuki Ito
  • Publication number: 20140212797
    Abstract: An actinic ray-sensitive or radiation-sensitive resin composition includes: (P) a resin that contains (A) a repeating unit capable of decomposing upon irradiation with an actinic ray or radiation to generate an acid in a side chain of the resin (P) and (C) a repeating unit represented by the following formula (I) as defined in the specification, wherein a polydispersity of the resin (P) is 1.20 or less.
    Type: Application
    Filed: March 28, 2014
    Publication date: July 31, 2014
    Applicant: FUJIFILM CORPORATION
    Inventors: Takeshi KAWABATA, Hideaki TSUBAKI
  • Publication number: 20140199617
    Abstract: A pattern-forming method includes in this order: step (1) of forming a film with an electron beam-sensitive or extreme ultraviolet radiation-sensitive resin composition that contains (A) a resin having an acid-decomposable repeating unit and capable of decreasing a solubility of the resin (A) in a developer containing an organic solvent by an action of an acid and (B) a low molecular weight compound capable of generating an acid upon irradiation with an electron beam or extreme ultraviolet radiation and decomposing by an action of an acid to decrease a solubility of the low molecular weight compound (B) in an organic solvent; step (2) of exposing the film with an electron beam or extreme ultraviolet radiation; and step (4) of developing the film with a developer containing an organic solvent after the exposing to form a negative pattern.
    Type: Application
    Filed: March 27, 2014
    Publication date: July 17, 2014
    Applicant: FUJIFILM CORPORATION
    Inventors: Hideaki TSUBAKI, Hiroo TAKIZAWA, Takeshi KAWABATA
  • Patent number: 8732480
    Abstract: According to an embodiment, a memory management device increments a lower value of a first counter, updates the counter by incrementing an upper value and resetting the lower value when the lower value overflows, increments to update the lower counter value when the upper value is incremented as a result of writing a second data piece having the upper value in common to a memory, recalculates a first secret value calculated using the first counter values and a root secret value in response to the first counter update, writes a first data piece and the first secret value to the memory, and at reading of the first data piece and the first secret value, calculates a second secret value using the updated first counter values and the root secret value, and compares the first secret value with the second secret value to verify the first data piece.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mikio Hashimoto, Hiroyoshi Haruki, Takeshi Kawabata, Tomohide Jokan, Yurie Fujimatsu, Ryotaro Hayashi, Fukutomo Nakanishi
  • Patent number: 8724804
    Abstract: According to an embodiment, a first linear transformation unit performs a linear transformation from mask data to first mask data. A second linear transformation unit performs a linear transformation from mask data to second mask data. A first calculator calculates first data based upon data to be processed and the first mask data. A selecting unit selects the first data or the second mask data. A non-linear transformation unit performs a non-linear transformation on the selected first data or second mask data. A second calculator calculates second data based upon the first data after the non-linear transformation and the mask data. A third linear transformation unit performs a linear transformation on the second data. The second data after the linear transformation by the third linear transformation unit is retained as new data to be processed, and the second mask data after the non-linear transformation is retained as new mask data.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: May 13, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Kawabata
  • Patent number: 8716868
    Abstract: A pad (15) is provided on a surface connecting a first substrate (11) of a lower layer module with an upper layer module, the pad is partially covered by an insulating film (20) to form an opening section (3) exposing the pad (15), a first connection terminal (2) is formed on the lower surface of the first substrate (11) of the lower layer module, the planar shape of the opening section (3) is different from the planar shape of the first connection terminal (2), the outer shape of the opening section (3) is larger than the first connection terminal (2), and in a transmissive inspection from above, the shape of the lower end of a second connection terminal (30) spreading in the opening section (3) is not concealed by the other terminal. This configuration enables easy and reliable determination of whether bonding sections are satisfactory by a non-destructive inspection.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: May 6, 2014
    Assignee: Panasonic Corporation
    Inventors: Takeshi Kawabata, Takashi Yui
  • Publication number: 20140103504
    Abstract: A first chip including electrodes is mounted above an expanded semiconductor chip formed by providing an expanded portion at an outer edge of a second chip including chips. The electrodes of the first chip are electrically connected to the electrodes of the second chip by conductive members. A re-distribution structure is formed from a top of the first chip outside a region for disposing the conductive members along a top of the expanded portion. Connection terminals are provided above the expanded portion, and electrically connected to ones of the electrodes of the first chip via the re-distribution structure.
    Type: Application
    Filed: December 27, 2013
    Publication date: April 17, 2014
    Applicant: Panasonic Corporation
    Inventors: HIROKI YAMASHITA, TAKASHI YUI, TAKESHI KAWABATA, KIYOMI HAGIHARA, KENJI YOKOYAMA
  • Publication number: 20140103502
    Abstract: A semiconductor device includes: a first semiconductor chip held on a substrate and including an expanded portion expanding outward from a side surface of a body of the first semiconductor chip; a first wire connecting the expanded portion of the first semiconductor chip to the substrate; and a second wire connecting the body of the first semiconductor chip to the substrate.
    Type: Application
    Filed: December 18, 2013
    Publication date: April 17, 2014
    Applicant: Panasonic Corporation
    Inventors: Kenji Yokoyama, Takeshi Kawabata
  • Publication number: 20140103536
    Abstract: A semiconductor device includes: on an upper surface of a second semiconductor chip on a circuit board, a ring dam section formed at an outer circumference of a mounting region above which a first semiconductor chip is mounted; and an interconnect extending from the dam section to a center section of the first semiconductor chip or the second semiconductor chip in a region in which the first semiconductor chip faces the second semiconductor chip. The interconnect is electrically connected to a connection terminal on a circuit formation surface of the first or second semiconductor chip at the center section of the first or second semiconductor chip. The dam section and the interconnect are power supply interconnects or ground interconnects.
    Type: Application
    Filed: December 18, 2013
    Publication date: April 17, 2014
    Applicant: Panasonic Corporation
    Inventors: Kenji Yokoyama, Takeshi Kawabata
  • Publication number: 20140103544
    Abstract: A semiconductor device includes an extended semiconductor chip including a first semiconductor chip and an extension outwardly extending from a side surface of the first semiconductor chip; and a second semiconductor chip connected to the extended semiconductor chip through a plurality of bumps and electrically connected to the first semiconductor chip. The first semiconductor chip is smaller than the second semiconductor chip. At least one external terminal is provided on the extension.
    Type: Application
    Filed: December 26, 2013
    Publication date: April 17, 2014
    Applicant: Panasonic Corporation
    Inventors: KENJI YOKOYAMA, TAKESHI KAWABATA, KIYOMI HAGIHARA
  • Publication number: 20140099572
    Abstract: According to one embodiment, an actinic-ray- or radiation-sensitive resin composition includes a compound (P) containing at least one phenolic hydroxyl group and at least one group with a phenolic hydroxyl group whose hydrogen atom is replaced by any of groups of general formula (1) below.
    Type: Application
    Filed: December 12, 2013
    Publication date: April 10, 2014
    Applicant: FUJIFILM Corporation
    Inventors: Takeshi INASAKI, Takeshi KAWABATA, Tomotaka TSUCHIMURA
  • Patent number: 8619976
    Abstract: An encryption/decryption method comprises by using a generalized Feistel structure in which data is divided into n pieces and mixing processing with key data is performed, diffusion processing, in which data transformation via linear operation is executed, is performed at least once between rounds of the generalized Feistel structure, wherein. As the diffusion processing, linear transformation is performed in which each of n pieces of output data is operated on by two or more pieces of input data. The method is adapted for encryption or decryption.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: December 31, 2013
    Assignees: NEC Corporation, NEC Software Hokuriku, Ltd.
    Inventors: Tomoyasu Suzaki, Yukiyasu Tsunoo, Hiroyasu Kubo, Maki Shigeri, Teruo Saito, Takeshi Kawabata, Hiroki Nakashima
  • Patent number: 8603727
    Abstract: An active light ray sensitive or radioactive ray sensitive resin composition which satisfies high sensitivity, high resolution, good pattern configuration, and good line edge roughness at the same time to a great extent, while having sufficiently good outgassing performance during exposure, and an active light ray sensitive or radioactive ray sensitive film formed by using the composition, and a pattern-forming method, are provided. The active light ray sensitive or radioactive ray sensitive resin composition according to the present invention includes a resin (P) containing a repeating unit (A) which decomposes by irradiation with active light ray or radioactive ray to generate an acid, and a repeating unit (C) containing a primary or secondary hydroxyl group.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: December 10, 2013
    Assignee: FUJIFILM Corporation
    Inventors: Takeshi Kawabata, Hidenori Takahashi, Tomotaka Tsuchimura, Shuji Hirano, Hideaki Tsubaki
  • Patent number: 8552549
    Abstract: In a substrate for a stacking-type semiconductor device including a connection terminal provided for a connection with a semiconductor chip to be stacked and an external terminal connected to the connection terminal through a conductor provided in a substrate, connection terminals of a power supply, a ground and the like, which terminals have an identical node, are electrically continuous with each other. Thus, it is possible to facilitate an inspection of electrical continuity between each connection terminal and an external terminal corresponding to each connection terminal by minimum addition of inspecting terminals. Further, it is possible to improve reliability of a stacking-type semiconductor module.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: October 8, 2013
    Assignee: Panasonic Corporation
    Inventors: Masatoshi Shinagawa, Takeshi Kawabata
  • Publication number: 20130236005
    Abstract: According to an embodiment, a cryptographic processing apparatus performs processes to encrypt plain text or decrypt cipher text. The processes include a non-linear process using multiplication. The non-linear process is a process performed using intermediate data masked with mask data. The intermediate data is data in a middle of the plurality of processes. The mask data hides the intermediate data. The apparatus includes a non-linear processing unit configured to receive first data that is an exclusive OR of a product of the intermediate data and first mask data and second mask data, and output second data that is an exclusive OR of a product of data obtained by the non-linear process on the intermediate data and data obtained by the non-linear process on the first mask data and third mask data having a predetermined correspondence relation with the second mask data.
    Type: Application
    Filed: February 15, 2013
    Publication date: September 12, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hanae Ikeda, Takeshi Kawabata
  • Publication number: 20130219408
    Abstract: According to an embodiment, a computer program product includes a computer-readable medium including program, when executed by a computer, to have a plurality of modules run by the computer. The computer includes a memory having a shared area, which is an area accessible to only those modules which run cooperatively and storing therein execution module identifiers. Each of the modules includes a first operation configured to store, just prior to a switchover of operations to an other module that runs cooperatively, an identifier of the other module as the execution module identifier in the shared area; and a second operation configured to execute, when the execution module identifier stored in the shared area matches with an identifier of own module immediately after a switchover of operations from the other module, a function inside the own module.
    Type: Application
    Filed: August 15, 2012
    Publication date: August 22, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyoshi HARUKI, Mikio HASHIMOTO, Fukutomo NAKANISHI, Ryotaro HAYASHI, Yurie FUJIMATSU, Tomohide JOKAN, Takeshi KAWABATA
  • Patent number: 8499306
    Abstract: A microprocessor executes programs in a pipeline architecture that includes a task register management unit that switches a value of a task register to second register information that is used when a second task is executed after the execution of a first task is completed, if a switch instruction to the second task is issued when a plurality of units executes the first task, and a task manager that switches a value of a task identification information register to a second task identifier after the value is switched to the second register information, and grants each of the plurality of units permission to execute the second task.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: July 30, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyoshi Haruki, Mikio Hashimoto, Takeshi Kawabata