Abstract: An automatic design system for designing wirings on circuit elements, includes an input device configured to receive circuit information, a glitch searching unit configured to search a glitch-occurring circuit element, a skew calculator configured to calculate a skew of a clock signal, a circuit information analyzer configured to define the calculated skew as a first target skew and determine whether the glitch can be reduced by setting the first target, a first target skew setting unit configured to set the first target, and a first latch insertion unit configured to insert a first latch.

Abstract: An automatic circuit design apparatus includes a setting module configured to set an upper limit electric potential of a virtual ground line in a circuit to be designed, by use of a cell library for low-threshold cells, a cell library for high-threshold cells, and information of the circuit to be designed. A layout generator is configured to generate a layout based on the information, the cell library for low-threshold cells, and the cell library for high-threshold cells.

Abstract: A logic circuit design equipment and a logic circuit design method include analyzing input states of all of first cells, respectively, analyzing leakage currents of all of first cells in a case where each first cell is high Vth cell showing a small leakage current at a low speed operation and low Vth cell showing a large leakage current at a high speed operation, respectively, and substituting the first cells for second cells within a range satisfying a timing restriction. Herein, a threshold of the second cell is different from a threshold of the first cell.

Abstract: An automatic design system for designing wirings on circuit elements, includes an input device configured to receive circuit information, a glitch searching unit configured to search a glitch-occurring circuit element, a skew calculator configured to calculate a skew of a clock signal, a circuit information analyzer configured to define the calculated skew as a first target skew and determine whether the glitch can be reduced by setting the first target, a first target skew setting unit configured to set the first target, and a first latch insertion unit configured to insert a first latch.

Abstract: A computer aided design technique for clock gated logic circuits effective to reduce the electric power consumption is disclosed.

Abstract: A computer aided design system and a method for clock gated logic circuits, a computer-readable medium for storing the same and a gated clock circuit are provided in which the clock skew is suppressed within a tolerable level without increasing the electric power consumption.

Abstract: A low power test circuit and a semiconductor integrated circuit are provided, i.e., the low power test circuit comprises a first stage single phase scan flip flop, a second stage single phase scan flip flop, a delay element located between an output terminal of the first stage single phase scan flip flop and an input terminal of the second stage single phase scan flip flop, a gate circuit connected between the output terminal of the first stage single phase scan flip flop and the delay element, and the gate circuit transferring scan data from the output terminal of the first stage single phase scan flip flop to the delay element in a scanning test mode thus reducing power dissipation in the delay element. The semiconductor integrated circuit comprises a shift register comprising a plurality of single phase scan flip flop serially connected and the low power test circuit.

Abstract: A computer aided design system and a method for clock gated logic circuits, a computer-readable medium for storing the same and a gated clock circuit are provided in which the clock skew is suppressed within a tolerable level without increasing the electric power consumption.

Abstract: A logic circuit design equipment has a state analysis section, a leakage current analysis section, and a cell substitution section. The state analysis section has a function of analyzing input states of all of first cells, respectively. The leakage current analysis section has a function of analyze leakage currents of all of first cells in a case where each first cell is high Vth cell showing a small leakage current at a low speed operation and low Vth cell showing a large leakage current at a high speed operation, respectively. The cell substitution section has a function of substituting the first cells for second cells within a range satisfying a timing restriction. Herein, a threshold of the second cell is different from a threshold of the first cell.

Abstract: Information about logic circuit not clock-gated, information about enable logic for controlling clock output and information about a gating circuit are inputted through circuit information I/O portion. Enable logic timing constraint generating portion generates timing constraint to be secured for enable logic. Enable logic timing determination portion calculates a delay time in the enable logic and determines whether or not the enable logic satisfies the timing constraint based on the delay time. Clock gating execution portion, when the enable logic satisfies the timing constraint, adds a gating circuit and a circuit composed of the enable logic to a logic circuit not clock-gated so as to generate a clock-gated logic circuit. Circuit information I/O portion outputs information about the clock-gated logic circuit and timing constraint to be secured for the enable logic.

Abstract: An automatic circuit generation system for generating an object circuit by the use of a cell library including logic cells is described. The system comprising a node state analyzing unit which is configured to obtain combinations of input signals to exchangable input pins of a logic cell of the cell library included in the object circuit and the probabilities of the respective combinations of the input signals; a leakage current estimating unit which is configured to determine a combination of the input signals, with which the leakage current passing through the logic cell of the cell library included in the object circuit is minimized, with reference to information about leakage currents passing through the exchangable input pins of the logic cell of the cell library included in the object circuit; and an output unit which is configured to output circuit information in accordance with the combination of the input signals as obtained by the leakage current estimating unit.

Abstract: Antenna diodes reduction. The number of antenna diodes is reduced in order to achieve an improved integrated circuit (IC) performance in terms of speed and power consumption. Essentially, before the number of antenna diodes can be reduced interconnect segments at a metal layer and metal layers below it are checked to find out if there are any segments of interconnects to gate inputs that are not yet connected to an output of a signal source. Further, a ratio is established for each segment of interconnect to gate input(s) that is not yet connected to an output. The ratio relates to the physical characteristics of the gate and interconnect and is expressed as the relationship between the gate area and area of the interconnect segments that are not yet connected to the signal source. The ratio is then compared against a set criteria such as an upper limit of the ratio.

Abstract: Information about logic circuit not clock-gated, information about enable logic for controlling clock output and information about a gating circuit are inputted through circuit information I/O portion. Enable logic timing constraint generating portion generates timing constraint to be secured for enable logic. Enable logic timing determination portion calculates a delay time in the enable logic and determines whether or not the enable logic satisfies the timing constraint based on the delay time. Clock gating execution portion, when the enable logic satisfies the timing constraint, adds a gating circuit and a circuit composed of the enable logic to a logic circuit not clock-gated so as to generate a clock-gated logic circuit. Circuit information I/O portion outputs information about the clock-gated logic circuit and timing constraint to be secured for the enable logic.

Abstract: A computer aided design technique for clock gated logic circuits effective to reduce the electric power consumption is disclosed.

Abstract: A computer aided design technique for clock gated logic circuits effective to reduce the electric power consumption is disclosed.

Abstract: An instruction flow control circuit controls the selection and execution of instruction signals in a microprocessor having multiple execution units that can execute plural instructions at one time. The instruction flow control circuit compares a number of signals indicating how many execution units are available with a number of signals indicating how many execution units are required. The circuit is a matrix of transmission gates which propagate signals through, or shift signals between, various signal paths for available resources, depending on the signals requesting the executing units. A number of output gates suppress the execution of instruction signals where an execution unit is requested but none are available.

Abstract: A fetching operation break unit breaks a fetching operation of a block data from a main memory, when a system bus is released during the fetching of the block data and also when data written due to a write access by an external device into the main memory coincides with the fetching of one block data. Further, a notification means notifies the state of the fetching operation to an external cache memory. Therefore, the external cache memory can confirm whether a block-in operation of the microprocessor is broken or not, and the contents of the external cache can correctly coincide with the contents of the internal cache and the main memory by carrying out a steal operation, so that the operational reliability of a computer system can be increased.

Abstract: A pair of saddle type horizontal deflection coils are provided at those upper and lower places on the inner wall of the coil separator. Vertical deflection coils toroidally wound on a core are provided on the outer periphery of the coil separator. Neck-side magnetic pieces are provided at those upper and lower sides of the neck-side area between the coil separator on one hand and the vertical deflection coils on the other hand. A pair of magnetic pieces, right and left, are provided, as a pair of crossarms, on the coil separator at a front-side section. In a deflection yoke apparatus thus provided, magnetic field creation areas at the crossarms are provided mainly on a Y axis side and four permanent magnets are provided on the front-side flange section of the coil separator at an angle of about 10.degree. relative to an X axis so that these permanent magnets are magnetized substantially in a tube direction of a CRT.

Abstract: A comparing unit compares an address of data written into a main memory by an external device with an address of data stored in a cache memory, and a masking unit masks specific bits obtained by a result in said address comparing unit. An invalidating unit invalidates data stored in the cache memory corresponding to the specific bits masked by the masking unit. Therefore, inconsistency between the main memory and the cache memory can be prevented, even when the data are transferred by using a block transfer process.

Abstract: Disclosed is a test assistant system for a logical design process comprising a description storage data base for storing statements expressing logical functions of circuit components to be tested, a compiler for compiling the statements to output object data, a data base for storing the object data, a test pattern generator for generating test patterns by using the object data stored in the data base, a test pattern data base for storing the test patterns, each having a level number, a simulator for executing a simulation for the logical function by using the test patterns stored in the test pattern data base, and a display for displaying the object data, the test patterns, the information used in the simulation, and relationships among them.