Abstract: A plurality of solar batteries are provided between a first substrate and a second substrate. The first substrate and the second substrate are formed of, for example, a paper or a non-woven cloth, which is a material including a natural fiber, cellulose, as the main component. Papers and silicon have relatively small difference in coefficient of thermal expansion so that warp caused by changes in the temperature is suppressed. Also, papers are light, easy to be processed and spontaneously decomposed so that disposing becomes easy. The first substrate is preferable to be transparent or semitransparent and preferable to be formed of cellophane paper, glassine paper, parchment paper, or Japanese paper. Oil may be included in the material. The second substrate is preferable to be opaque. A waterproof film may be formed on the first substrate and the second substrate.

Abstract: A plurality of solar batteries are provided between a first substrate and a second substrate. The first substrate and the second substrate are formed of, for example, a paper or a non-woven cloth, which is a material including a natural fiber, cellulose, as the main component. Papers and silicon have relatively small difference in coefficient of thermal expansion so that warp caused by changes in the temperature is suppressed. Also, papers are light, easy to be processed and spontaneously decomposed so that disposing becomes easy. The first substrate is preferable to be transparent or semitransparent and preferable to be formed of cellophane paper, glassine paper, parchment paper, or Japanese paper. Oil may be included in the material. The second substrate is preferable to be opaque. A waterproof film may be formed on the first substrate and the second substrate.

Abstract: A semiconductor substrate, a thin film semiconductor device, a manufacturing method thereof and an anodizing apparatus which can reduce the manufacturing cost and save the resources are provided. According to this invention, a semiconductor thin film is formed through a separation layer of a porous semiconductor on a substrate body of sapphire; the semiconductor thin film is separated from the porosity layer and used for a thin film semiconductor device; and the substrate body from which the semiconductor thin film is separated is used again after the separation layer attached thereto is removed by etching. Since sapphire has high strength, high rigidity, high resistance to wearing, high heat resistance, high abrasion resistance and high chemicals resistance, no deterioration and no damage occur even when the substrate body is repetitively used. Thus, the recycle frequency can be increased, and the reduction of the manufacturing cost and the saving of the resources can be promoted.

Abstract: The present invention is a computer aided design (CAD) system in which graphic drawings are generated by the user selecting and placing figures representing objects such as walls and doors on a screen. This is accomplished using a command selecting unit that selects a command for placing an object of a desired shape in a desired position. Once the command is selected a parameter managing unit is engaged. This parameter managing unit holds parameters used to execute the selected command and also displays values set for the parameters in a parameter field on a display screen. The user may also enter desired values for the parameters using a parameter entering unit. In response to a user request to execute a command, a command executing unit determines the position and shape of the object using the values set for the parameters, and places the object in the proper location of the drawing display area.

Abstract: A three-dimensional integrated circuit device incorporating any two-dimensional LSIs, such as CCD, MOS-type imaging device and DRAM using trench-type capacitors as its memory cell, can be manufactured economically. Each two-dimensional LSI is prepared by first forming a single-crystal silicon layer on a single-crystal silicon substrate via a porous silicon layer and thereafter forming the two-dimensional LSI on the single-crystal silicon layer. After a support substrate is bonded to the surface of the two-dimensional LSI, the two-dimensional LSI is detached from the single-crystal silicon substrate along the porous layer, and subsequently stacked on another two-dimensional LSI formed on another single-crystal silicon substrate by bonding the bottom surface of the former to the top surface of the latter.

Abstract: A semiconductor memory having storage cells each consisting of a MIS transistor and a capacitor, and a method of manufacturing the same. The semiconductor memory comprises a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and semiconductor regions formed on the surface of the insulating layer. The semiconductor memory is characterized in that the MIS transistors are formed, respectively, on the surfaces of the semiconductor regions and separated from each other and from the semiconductor substrate by an insulating layer, and the capacitors are formed, respectively, under the corresponding MIS transistors. The insulating layer separating the MIS transistors from each other and from the semiconductor substrate reduces current leakage between the storage cells and reduces capacitance across bit lines formed on the side of the MIS transistors and the semiconductor substrate.

Abstract: In a method of finishing a surface of a floating type magnetic head in which a sliding contact surface opposing a magnetic recording medium is made of a polycrystal material comprising at least two kinds of phases of different compositions mixed together, the sliding contact surface is roughened by treatment with an etching solution in accordance with a chemical etching process. The sliding contact surface of the floating type magnetic head can be mirror-finished with an appropriate surface roughness, so that satisfactory CSS performance and good electromagnetic performance can be obtained. The sliding contact surface is preferably made of a polycrystal ceramic material selected from the CaTiO.sub.3 ceramic system, the AlTiC ceramic system and the MnO-NiO ceramic system. The etching solution contains aqueous hydrogen peroxide as an oxidizing agent and is preferably an aqueous hydrogen peroxide and ammonia solution.

Abstract: A porous Si layer is formed on a single-crystal Si substrate, and then a p.sup.+ -type Si layer, p-type Si layer and n.sup.+ -type Si layer which all make up a solar cell layer. After a protective film is made on the n.sup.+ -type Si layer, the rear surface of the single-crystal Si substrate is bonded to a tool, and another tool is bonded to the front surface of the protective film. Then, the tools are pulled in opposite directions to mechanically rupture the porous Si layer and to separate the solar cell layer from the single-crystal substrate. The solar cell layer is subsequently sandwiched between two plastic substrates to make a flexible thin-film solar cell.

Abstract: A SOI substrate fabricating method comprises the steps of: making a first etch-stop layer on a silicon substrate; polishing the surface of the first etch-stop layer; making a silicon buffer layer on the polished surface of the first etch-stop layer; making a silicon layer on the silicon buffer layer; making an insulating layer on the silicon layer; bonding one of major surfaces of a support substrate onto the insulating layer; and removing the silicon substrate, the first etch-stop layer and the silicon buffer layer and maintaining the insulating layer and the silicon layer on the one surface of the support substrate.

Abstract: An electronic part, specifically a red-eye prevention lamp, is suspended in a gap between immediately adjacent curved internal walls of a camera. The curved internal walls are those of a battery compartment and a film storage compartment. The red-eye prevention lamp is suspended by a control circuit board bridging the curved walls.

Abstract: A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.3, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.

Abstract: A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.3, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.

Abstract: A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.3, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.